Design Engineer II

Responsibilities RTL 2 GDSII implementation of in‑house IP and external customer designs. Development, automation and maintenance of EDA flows and scripts for physical implementation. Develop TFM to optimize PPA for IP’s and Soft Controllers. PPA characterization and optimization of flow for performance‑oriented and power‑oriented best‑in‑class IP cores in advanced process nodes on TSMC, Intel, Samsung and Rapidus Foundries. Digital design implementation using Cadence EDA tools – Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools. Solid scripting skills including Python and Tcl. Qualifications MS/MTech/BE/BTech in Electronics from reputed institutes with 2+ years experience. Physical design experience in an ASIC design environment. Knowledge of the complete ASIC design flow: synthesis, physical design, timing analysis, power analysis and formal verification. Excellent leadership, communication, analytical and problem‑solving skills. Self‑motivated and a good team player. Salary & Benefits The annual salary range for California is $87,500 to $162,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Our benefits programs include paid vacation and paid holidays, a 401(k) plan with employer match, an employee stock purchase plan, and a variety of medical, dental and vision plan options. Equal Employment Opportunity Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy ( Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability or any other protected class. #J-18808-Ljbffr