Senior Hardware Design Engineer

About Unigen Unigen is a global technology company providing innovative electronics manufacturing and product solutions to customers across diverse industries. With decades of industry experience and operations in key global markets, we combine engineering expertise, advanced manufacturing capabilities, and responsive customer service to deliver reliable, high-quality solutions-from product development through production and fulfillment. Location and Work Arrangement This position is based in Newark, California and is onsite . Benefits Unigen offers a competitive compensation and benefits package. medical, dental, and vision coverage a 401(k) plan paid time off paid holidays professional development opportunities Benefits are subject to eligibility requirements and applicable plan terms. Job Details Location: Newark, CA Job Title: Senior Hardware Design Engineer Reports To: Sr. Director, Hardware & Systems Engineering Job Function: R & D Engineering Job Overview The Senior Hardware Design Engineer architectures, designs, and validates the next generation of high-performance computing platforms tailored for deep-learning infrastructure. This role owns the full lifecycle of complex, high-density PCBs, from schema capture to advanced board-level physical implementation. Positioned at the critical intersection of high-speed digital logic, severe power transience, and extreme thermal dynamics, the engineer ensures maximum system reliability for hyperscale AI deployments. Primary Responsibilities Accelerator System Design: Architect and implement high-density printed circuit board (PCB) for AI accelerator carrier cards, high-performance host boards, and deep-learning infrastructure. Design & Architecture: Own full-lifecycle schematic capture and design optimization for high-density, complex printed circuit boards. High-Speed Interface Engineering: Implement, simulate, and optimize high-speed digital and analog circuits using interfaces like DDR4, DDR5, and PCIe Gen 5/6. Power & Signal Integrity: Define and optimize robust board-level power distribution networks (PDN) capable of managing massive, transient current steps driven by modern AI logic gates. Thermal & Mechanical Reviews: Conduct joint architecture studies with thermal and mechanical engineers to balance extreme compute thermal dissipation with mechanical envelope constraints. Validation & Lab Bring-Up: Lead the hands-on bring-up, diagnostic debugging, and physical validation of complex pre-production accelerator hardware systems. Yield & Reliability Management: Drive root-cause analyses on structural anomalies discovered during test phases, applying corrective iterations to guarantee target field reliability inside hyperscale deployments. Qualifications Bachelor’s degree in electrical engineering or related field. 10+ years of experience as electrical engineer designing high speed digital and analog circuitry on complex high density printed circuit board. 5+ years of experience in designing high density boards with fine pitch components and high-density connectors, including expertise in high-speed interfaces such as DDR4, DDR5, PCIe Gen5/6 and microcontrollers and processors. Hand-on experience accomplishing system level validation in complex hardware/software environment. Strong hand-on debugging skills across system, firmware and hardware domains. Proficiency with scripting/programming in python, C or similar languages and understanding product validation methodologies, such as EVT and DVT. Preferred Qualifications DDR4/5 modules, SSD and enterprise storage products design and validation experience. Strong understanding of high speed SERDES, equalization technology and PCIe protocols. Strong debugging experience using lab tools such as protocol analyzers, oscilloscopes and logic analyzers. Mentoring experience or technical leadership in validation team. Familiarity with industry certifications, compatibility testing and qualification processes. Proficient in collaborating with teams and suppliers to deliver quality products on tights schedules. #J-18808-Ljbffr