Hybrid Senior Mixed-Signal IP Enablement & Debug Engineer
Intel
Intel is seeking an experienced engineer to join their Hard IP Development Group in Folsom, California. The role involves partnering with SoC customers and executing test plans using AI-driven tools, as well as leading IP debugging during silicon bring-up. Applicants should have a relevant degree and significant experience in IP Integration, with strong skills in signal integrity and debugging processes. A competitive compensation package and hybrid work options are available. #J-18808-Ljbffr Intel
Vacancy posted 2 days ago
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