System Performance Modeling Engineer/Architect (NPU)

Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud.

You will build the models that tell us how fast the chip will actually run before any RTL exists, and keep telling us as the design evolves. Working at full-chip scope, you will model the EtHash tile array, the self-developed NoC, the 3D-DRAM bandwidth path. Your models drive the biggest architecture decisions: how many tiles, how much local memory, what NoC bandwidth and what memory QoS are needed to hit our performance targets within the power and thermal envelope. You will be the quantitative conscience of the architecture team and a close partner to the hash core, memory and compiler groups.

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Key responsibilities:**

• Full-chip performance models - build and maintain cycle-approximate / analytical models of the tile array, NoC and memory subsystem in C++/SystemC and Python.


• Workload & roofline analysis - produce roofline and bottleneck analyses that map workloads onto the tile array and memory hierarchy.


• Traffic & contention modeling - model NoC contention, memory bandwidth and QoS under realistic traffic; generate and parameterize traffic scenarios for architecture studies.


• Architecture trade-offs - run sweeps (tile count, local-memory size, NoC topology/bandwidth, memory channels/QoS) and turn results into clear recommendations that feed the architecture freeze.


• Correlation & validation - correlate model predictions against RTL, emulation/FPGA and (later) silicon; quantify and close the modeling-to-reality gap.


• Golden-reference hooks - provide performance references and golden-model hooks used by the performance and verification teams for sign-off.


• Reporting - maintain dashboards and trade-off decks that make performance risk visible to architecture and program leadership

• 5+ years in performance modeling / architecture for SoCs and accelerators.


• Strong C++ and Python; experience with SystemC or a comparable cycle-approximate modeling framework.


• Solid grasp of computer architecture fundamentals: memory hierarchy, bandwidth/latency trade-offs, interconnect/NoC behavior and roofline reasoning.


• Demonstrated ability to model a subsystem and turn results into architecture decisions, not just numbers.


• Comfortable working from incomplete specs and collaborating across architecture, design and software teams.

• Familiarity with NoC/interconnect modeling, memory-controller behavior or 3D-DRAM/HBM bandwidth analysis.


• Exposure to compiler/dataflow co-design for accelerators.


• Experience correlating models against RTL, emulation or silicon.


• Background with tile-based or dataflow architectures.

• A trusted full-chip performance model that the team uses to make tile-count, NoC and memory decisions at architecture freeze.


• Quantified, agreed performance targets and a documented modeling-vs-reality correlation plan.


• Performance trade-off reporting that program and architecture leadership rely on.

• A culture that values authenticity and diversity of thoughts and backgrounds;


• An inclusive and respectable environment with open workspaces and exciting start-up spirit;


• Fast-growing company with the chance to network with industrial pioneers and enthusiasts;


• Ability to contribute directly and make an impact on the future of the digital asset industry;


• Involvement in new projects, developing processes/systems;


• Personal accountability, autonomy, fast growth, and learning opportunities;


• Attractive welfare benefits and developmental opportunities such as training and mentoring.