Senior Electrical Engineer, ASIC Technical Lead

About the Company

Synchron’s vision is to build non-surgical brain–computer interfaces at global scale that protect the fundamental human rights of freedom of expression and autonomy. Our first mission is to develop motor decoders that restore the ability of 15 million people with paralysis to interact with the digital world. Our second mission is to develop whole-brain cognitive decoders that enable hundreds of millions of people with cognitive decline to preserve and expand their agency as cognition changes over time. In pursuing these goals, we aim not only to help humans flourish, but also to drive fundamental discoveries in human intelligence. Our team operates at the intersection of healthcare and technology, translating breakthrough research into real-world, safety-critical systems.

About the Role

Senior Electrical Engineer, ASIC Technical Lead

Synchron is developing a high-channel-count neural recording ASIC in partnership with an external IC design house, and we are looking for an experienced engineer to own the chip’s technical delivery. Although our partner owns design, simulation, test, and fabrication, this role is accountable for the chip meeting spec and shipping - including catching problems when the partner's work doesn't.

This role is the internal technical authority on our cutting-edge neural recording chip: the person technically fluent enough to hold our partner to an airtight specification, independently judge whether their design and simulation work is sound, and gate the program at every major decision point (architecture review, pre-tapeout sign-off, and post-silicon disposition). You're not doing the partner's design work; you're making sure it's correct, on-spec, and defensible

You will have been through at least one ASIC tapeout before (ideally several) so you know firsthand what separates a design review that catches real problems from one that rubber-stamps a partner's summary slide. You hold yourself and others to a high standard and have a proven track record of successfully delivering silicon.

Key Responsibilities

• ASIC requirements and specification: author and maintain the versioned, traceable requirements and specification document that is the single source of truth between us and the design partner.
• Design & architecture reviews: run technical reviews with the partner at each gate — block-level, top-level, pre-tapeout — and independently assess their schematics, netlists, and simulation results rather than accepting a summary.
• Simulation & sign-off: review SPICE/Cadence simulation results, DRC/LVS, and DFT plans; own the tapeout readiness checklist and make the go/no-go call.
• Risk register: track and own design-level risks — process corners, matching, noise budget, power budget across the full channel count — and drive them to closure.
• First-silicon bring-up: partner with the AFE Test & Integration Engineer during bring-up; when results are out of spec, lead root-cause to determine whether it's a test artifact, a marginal corner, or a real silicon bug.
• Respin leadership: if a respin is required, lead the design review of the fix and the re-verification plan.
• Sustaining & roadmap: once qualified, own engineering change orders, risk file / FMEA updates from field or test data, and the specification for any next-generation chip (higher channel count, lower power, new features).

Required Skills and Qualifications

Education: B.S. or M.S. in Electrical Engineering (or equivalent) with a silicon design emphasis.

Experience: 5+ years of experience in ASIC/SoC design and development, with at least one full ASIC development cycle from concept to silicon.

Technical Skills:

• Strong analog or mixed-signal IC design or verification background; comfortable reading and critiquing someone else's schematics and simulations, not only producing your own.
• Working fluency with SPICE/Cadence-class simulation review, DRC/LVS, and DFT concepts.
• Experience working with an external design partner, foundry, or fab — you understand where partner incentives and program incentives can diverge, and how to write a spec that closes those gaps.
• Nice to have: experience in a regulated medical device environment (design controls, DHF, 510(k)/PMA) or with implantable-class electronics.

Pay range and compensation package

• The base salary range for this role is $180,000 and $220,000 per year and stock option or restricted stock units grants, depending on experience, skills, and qualifications.

Additional Benefits

• Benefits (for W-2, full-time, exempt employees in the US only) ***Intern positions not eligibleSubsidized medical and dental insurance coverage for you and your dependent(s)
• Life insurance, short-term disability, long-term disability
• 401k
• Discretionary unlimited PTO
• Flexible Spending Account for you and your dependent(s), with eligible plan elections
• Commuter benefits for NY employees

Visa Sponsorship

We are unable to offer visa sponsorship for this position at this time.

Equal Opportunity Statement

Equal Employment Opportunity (EEO) Synchron is an equal opportunity employer. We are committed to creating an inclusive environment for all employees and applicants and provide equal employment opportunities without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity or expression, national origin, age, disability, genetic information, marital status, veteran status, or any other characteristic protected by applicable law.If you need a reasonable accommodation during the application or interview process, please let us know.

Join Us!

At Synchron, you will be part of a transformative mission, and you will work alongside driven people who believe in the power of collaboration and innovation to make a lasting impact. If you are excited to stretch your skills and contribute to something meaningful, apply now and build the future with us.