Senior SOC Verification Engineer (SystemVerilog/UVM)
Apple
A leading technology company in Santa Clara is looking for a Design Verification Engineer to ensure the functionality and performance of their SOCs. The role involves developing test plans, collaborating with design teams, and verifying various hardware components. The ideal candidate has a BS degree and at least 10 years of relevant industry experience. This position offers a competitive salary and comprehensive benefits, including stock options and educational reimbursements. #J-18808-Ljbffr
Vacancy posted 4 hours ago
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