Senior RTL Design Engineer AI-Driven Silicon & FPGA

AMD is seeking a passionate HW architect for FPGA/ASIC efforts in our San Jose hybrid environment. You will drive RTL design and verification for advanced IP blocks, work with DFT implementations, and collaborate across global teams to meet milestones. You should have strong Verilog/SystemVerilog skills, experience with EDA tools, and a solid foundation in ASIC/SoC development, including timing, floorplanning, and test. #J-18808-Ljbffr