Senior Power Engineer, ASIC at Waymo - Mountain View, CA, USA

Senior Power Engineer, ASIC at Waymo – Mountain View, CA, USA Waymo is an autonomous driving technology company with the mission to be the most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World’s Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo One, a fully autonomous ride‑hailing service, and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over one million rider‑only trips, enabled by its experience autonomously driving tens of millions of miles on public roads and tens of billions in simulation across 13+ U.S. states. Waymo’s Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle’s software stack. To achieve our mission, we architect and create high‑performance custom silicon; we develop system‑level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world’s highest performance automotive compute platforms. In this hybrid role, you’ll report to an ASIC Design Manager You will: Work with architects and end users to translate application requirements into power specifications Architect power management & efficiency solutions at the chip and subsystem‑level Specify, micro‑architect and implement power solutions for power‑critical subsystems, such as ML accelerators Perform power, performance analyses of key blocks to identify optimization opportunities in logic design and physical design Define methodology for predicting, measuring, correlating and rolling up power pre and post silicon Collaborate with cross functional teams to define package and board level power delivery strategy You have: BS degree in Computer Engineering or equivalent practical experience 7+ years of industry experience with Verilog and SystemVerilog, RTL digital microarchitecture Deep knowledge of chip‑level and block‑level power analysis tools and methodology Fluency in at least one high level programming language such as Python or C++ Experience working cross‑functionally with Software, Architecture, Physical Design and Package teams Familiarity with on‑chip power management solutions including voltage‑frequency scaling, and transient power management We prefer: Master’s or PhD degree in Engineering Proven ability to architect and deliver power management solutions for high performance computing cores such as CPU/GPU/NPU Experience crafting benchmarks for power analysis and correlation Experience with the full digital design cycle — from spec through bring‑up #LI-Hybrid The expected base salary range for this full‑time position across US locations is listed below. Actual starting pay will be based on job‑related factors, including exact work location, experience, relevant training and education, and skill level. Your recruiter can share more about the specific salary range for the role location or, if the role can be performed remote, the specific salary range for your preferred location, during the hiring process. Waymo employees are also eligible to participate in Waymo’s discretionary annual bonus program, equity incentive plan, and generous Company benefits program, subject to eligibility requirements. Salary Range$204,000—$259,000 USD #J-18808-Ljbffr Victrays