Principal Design Verification Engineer - CPU Core Hardware Prefetch

Overview

SiFive is seeking a Principal Design Verification Engineer to lead verification strategy and execution for CPU Core Hardware Prefetch in a high‑performance out‑of‑order core. This senior tech‑lead role focuses on advanced hardware prefetch verification, collaborating closely with architecture, RTL, performance, software, and verification teams to ensure design intent is captured and risks are identified early.

Responsibilities

• Lead verification planning and execution for CPU hardware prefetch functionality across unit‑level and core‑level strategy, debug, coverage closure, and sign‑off readiness.
• Define verification strategy, test plans, checkers, scoreboards, assertions, stimulus strategies, and coverage models for hardware prefetch microarchitecture and corner cases.
• Drive verification of hardware prefetch behaviors such as stream allocation and replacement, training from demand requests, prefetch generation, request replay and kill behavior, issue‑queue interactions, and feedback‑driven control of prefetch aggressiveness.
• Verify correctness of runtime configurability through prefetch CSRs, including enablement, windowing, distance thresholds, and queue‑allocation controls tied to L1/L2 cache and MSHR behavior.
• Verify interactions between the hardware prefetch engine and the memory hierarchy—DCache pipeline behavior, cacheable‑read‑only training conditions, MSHR fullness backpressure, L1/L2 prefetch targeting, and arbitration with other core traffic.
• Develop verification strategies for difficult corner cases such as stream misconfirmation, untraining, queue unavailability, threshold‑triggered throttling, page‑boundary behavior, multi‑stream behavior, and correctness under diverse operating modes and software‑programmed configurations.
• Use architectural counters, self‑checking tests, and microarchitectural observability to validate that prefetch behavior is functionally correct and robust across realistic performance‑sensitive traffic patterns.
• Partner with architects and designers from early feature‑definition stages to review specifications, identify ambiguity, improve debugability, and influence design from a verification perspective.
• Apply appropriate verification methods (simulation, formal techniques, emulation, performance‑oriented validation) for high‑risk or hard‑to‑observe hardware prefetch behaviors.
• Drive efficient failure analysis and root‑cause debugging across specification, RTL, test content, assertions, and verification infrastructure.
• Mentor engineers and shape reusable verification approaches, infrastructure, and methodology for future CPU core generations.

Minimum Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 12+ years of relevant experience in CPU/core or SoC functional verification, appropriate for a Principal / T6 role.
• Direct experience with out‑of‑order CPU core verification and strong understanding of CPU microarchitecture.
• Deep expertise in hardware prefetch verification or closely related CPU memory‑subsystem verification, with the ability to translate architectural intent into an effective verification strategy and execution plan.
• Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Strong debug skills and solid software or scripting fundamentals for building scalable DV infrastructure, automation, and analysis workflows.
• Strong understanding of CPU memory behavior, including ordering‑sensitive interactions, cache hierarchy effects, and how hardware prefetch interacts with demand traffic and system performance.

Preferred Qualifications

• Experience verifying advanced hardware prefetch architectures such as stride‑based or stream‑based prefetchers with training, confirmation, throttling, and adaptive distance control.
• Experience verifying prefetch engines integrated with DCache or memory‑subsystem pipelines, including interactions with issue queues, MSHRs, cache feedback, and replay behavior.
• Experience developing or reviewing verification content that uses performance counters, constrained‑random traffic, directed corner‑case scenarios, and software‑driven stress patterns to validate hardware prefetch correctness.
• Experience with formal verification to target bounded, control‑heavy, or interface‑sensitive microarchitectural problems.
• Experience using emulation or other acceleration techniques to improve turnaround on large CPU verification workloads.
• Experience collaborating effectively with performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.
• Demonstrated technical leadership through mentoring, methodology influence, and cross‑team execution on complex CPU verification efforts.

Success Criteria

• Hardware prefetch verification plans capture the real architectural and microarchitectural risks early and completely.
• Difficult bugs in prefetch training, stream management, queue behavior, throttling, page handling, and DCache interaction are found early, debugged efficiently, and closed with durable solutions.
• Verification quality improves across the broader CPU DV organization through stronger methodology, reusable infrastructure, and clear technical leadership.

Benefits

Variable/incentive compensation and/or equity may be included. The role is eligible for a comprehensive benefits package, which may include healthcare, retirement plans, paid time off, and other benefits. The position requires successful background checks, reference checks, and proof of eligibility to work in the United States of America. Export‑control compliance and export license requirements apply as per applicable laws.

Equal‑Opportunity Statement

SiFive is an equal‑opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. As an E‑Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I‑9, Employment Eligibility Verification, upon hire. We do not use E‑Verify to pre‑screen job candidates and will comply with all E‑Verify regulations.