Senior Design Verification Engineer

Design Verification Engineer Business Line Description: Advanced Chip Engineering's Digital IP team defines and develops components for a wide range of products, including automotive microprocessors, application processors, microcontrollers, and networking. The Austin Digital IP team develops components for DDR, display controller, high-speed serial links, DMAs, cores, memory controllers, and interconnect. Job Summary Defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications) and creating intelligent stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed test cases. Responsibilities Define and write IP verification plans based on requirements documents. Create intelligent stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed test cases. Define and write System Verilog Assertion (SVA) cover properties to match the verification plan. Write System Verilog (UVM) monitors, drivers, response checkers and SVAs for correctness. Develop and maintain portions of a verification environment including scripts and Make files. Debug failing test cases to determine source of failure (tool, test case, checker, Verilog RTL) and track resolution. Collect code and functional coverage results from random simulations, and analyze uncovered events to determine additional test scenarios needed to achieve 100% coverage. Perform assertion-based formal verification of blocks and IPs to ensure they meet requirements. Qualifications Minimum BSEE, BSCE, or BSCS. MSEE, MSCE, or MSCS a plus. Minimum 4 years of experience in IP or SoC design or verification. Hands‑on experience in using AI/ML tools for workflow and productivity improvements. Verilog, SystemVerilog, and UVM coding skills required. Verification skills (test planning, test case creation, test bench, simulation, debugging) required. Other programming skills (Python, C/C++, Perl, TCL, etc.) a plus. Design skills (design documentation, RTL coding, synthesis, static and formal checking, etc.) a plus. Knowledge of ARM AMBA protocols a plus. Ability to work independently and in small teams without close supervision required. Location Austin, TX EEO Statement NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals. #J-18808-Ljbffr NXP Semiconductors