SW engineer - Silicon CAD tool development

Job Details:Job Description: About the TeamIntel is seeking a motivated mid-level CAD/EDA Software Engineer to join the Silicon Chassis Automation Tool team. In this hands-on role, you will work closely with the tool lead to develop a chassis automation tool and own key subsystems.Chassis refers to non-compute infrastructure in any SoC, which provides essential platform services and typically includes interconnects, protocol bridges, clock/reset/power, security, debug/trace/analytics (DTA), RAS error logic, address maps, firmware tables, and more. The chassis automation tool collects user requirements and translates them into detailed parameters representing topology, then generates RTL, register definitions, integration, and verification collateral for the chassis using highly parameterized and configurable sub-components.Why This Role Is ExcitingBuild a brand new automation platform by defining the tool, schema, and methodology from the ground upDirectly influence next-generation SoC chassis architectures and deliveryPosition OverviewYou will work directly with the tool lead and partner with RTL design, verification, and SoC integration teams to code the architectural rules of the interconnect and develop a reliable, testable automation framework that produces expected results. AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected.Key ResponsibilitiesDevelop a chassis automation tool that meets requirements across multiple SoC programs, ensuring scalability, maintainability, and extensibilityUnderstand automation tool requirements and build tooling and infrastructure to translate those requirements into working code, generating outputs such as RTL, RDL, verification collateral, timing, and integration artifactsIntegrate with silicon frontend and backend tool flows to enable robust validation and quality checks across generated artifacts (e.g., RTL, Verilog, SDC, RDL), ensuring correctness and consistencyWork closely with the tool lead, architecture, RTL design, verification, and SoC integration teams to ensure the tool accurately produces outputs that meet downstream expectationsFollow and improve best practices in software design, testing, and maintainability, elevating overall team effectivenessSet up and maintain the CI /CD regression pipelineImplement specific rule functions, write unit tests, and extend coverage as neededYou should demonstrate the following professional traits to be successfulDetail-oriented and organized, with comfort owning well-scoped subsystems and delivering on clear milestonesCollaborative and communicative, able to work effectively across design, verification, and integration teamsExecution-focused, with a track record of consistent delivery against schedule and quality goalsQualifications:Minimum QualificationsBachelor's degree in Electrical Engineering, Computer Science, or a related field with 4+ years of experience in CAD/EDA tooling or design automation, or a Master's degree in a related field with 3+ years of experience3+ years of Python or a similar language, with hands-on experience building software systems or frameworks, including packaging, testing, and CLI tool developmentExperience designing and validating structured schemas using formats such as JSON or YAMLKnowledge of software engineering fundamentals including version control (Git), code reviews, unit/integration testing, and CI/CD practicesPreferred QualificationsUnderstanding of digital SoC design concepts, including RTL hierarchy, synthesis flows, and parameterized IP designWorking knowledge of SystemVerilog to understand and validate generated design outputsExperience with Network-on-Chip (NoC) architectures or high-performance interconnect protocols such as AXI, CHI, PCIe, UCIe, or similarFamiliarity with IP packaging, configuration, and integration methodologies, including standards such as IP-XACTExposure to industry EDA tools and design flowsKnowledge of graph-based algorithms or data structures relevant to topology generation, connectivity modeling, or routing problemsExperience in GUI development with modern UI frameworks such as Qt/QML, React, Electron etc.Strong understanding of object-oriented design, design patterns, and software architecture principles.Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $149,600.00-211,200.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.SummaryLocation: US, California, Santa ClaraType: Full time