Senior/Staff/Snr. Staff Design Verification (DV) Engineer

Design Verification Engineer Lattice Semiconductor is seeking a Design Verification Engineer to join the R&D organization. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow. Responsibilities Develop and review Test Plan based on design specification. Develop constrained‑random verification environment for complex DUT. Implement coverage metrics using cover point and assertion. Create and debug tests for DUT. Resolve bugs with remote designers. Requirements Strong understanding of verification process from test plan to coverage completion. Strong communication and analytical skills. Understanding of HDL (Verilog, SystemVerilog). Experience with designing with FPGA is a plus. Programming skills (C/C++, Perl, TCL or Python). Experience in high speed SERDES protocols (PCIe, Ethernet, CPRI or JESD204B/C, USB), Memory (DRAM, SRAM, Flash, DMA), Interconnect (AMBA AXI, AHB, APB), Peripherals (SPI, I2C or I3C, Flash), Video connectivity (MIPI, SDI, HDMI). BS/MS/PhD in Electronics or Computer Engineering and minimum of 5 years of SystemVerilog/UVM experience. Independent and self‑motivated, capable of executing under dynamic environment and uncertainties. Applications are welcome from all qualified candidates. #J-18808-Ljbffr Lattice