Sr. Staff/Principal GPU Engineer - Geometry/Tiler Microarchitecture

Sr. Staff/Principal GPU Engineer – Geometry/Tiler Microarchitecture Category: Algorithm & Architecture | Location: San Diego, CA | Experience: More than 8 Years Work Expe. Job Description About the TeamWith MediaTek’s leadership in SoC design, the MediaTek GPU IP team is committed to developing industry-leading, feature-rich, and highly PPA-competitive graphics IP. Our GPU technology is deployed across flagship and mainstream mobile SoCs and is also a foundational technology for adjacent markets including laptops, IoT, AI, VR/AR, automotive, and custom ASIC applications.The team is expanding and hiring top GPU talent across multiple disciplines, including architecture, microarchitecture, RTL design, software drivers, compiler technology, performance modeling, power optimization, and silicon validation. Positions are available in our San Diego and San Jose offices.Position OverviewWe are seeking a Senior Staff / Principal GPU Engineer specializing in Geometry and Tiler Microarchitecture to help define and develop next-generation GPU IP. The ideal candidate will have deep experience in graphics hardware architecture, microarchitecture specification, RTL implementation, performance analysis, and PPA optimization.In this role, you will drive the design and optimization of GPU geometry, tiling, binning, raster front-end, and cluster-level microarchitecture. You will collaborate closely with architecture, software, compiler, performance, RTL, verification, physical design, and post‑silicon teams to deliver best‑in‑class GPU IP for mobile, automotive, laptop, IoT, and ASIC markets. Role and Responsibilities Define and develop GPU cluster-level microarchitecture specifications for industry‑leading graphics IP. Lead microarchitecture design for GPU geometry and tiler‑related blocks, including primitive processing, tiling, binning, raster front‑end, scheduling, and workload distribution. Drive PPA optimization across power, performance, and area for complex GPU subsystems. Collaborate with architecture and software teams to translate product requirements, API behavior, workload characteristics, and performance targets into hardware specifications. Work closely with RTL design, verification, physical design, software, compiler, and performance teams to identify and resolve architectural, microarchitectural, and implementation bottlenecks. Analyze GPU workloads and performance data to optimize geometry throughput, tiler efficiency, memory bandwidth, cache locality, load balancing, and power efficiency. Guide GPU IP development through the full lifecycle, including microarchitecture definition, RTL implementation, verification, synthesis, timing closure, tape‑out, bring‑up, and post‑silicon debug. Debug and resolve complex pre‑silicon and post‑silicon issues related to functionality, performance, power, and area. Influence future GPU architecture directions through technical analysis, workload studies, performance modeling, and competitive benchmarking. Apply AI‑assisted tools and automation to improve productivity in RTL development, functional debug, performance analysis, and PPA exploration. Deliver high‑quality technical results while meeting project milestones, schedules, and product requirements. Build trusted and effective working relationships across internal teams, external partners, and cross‑site engineering organizations. Contribute to best‑in‑class GPU IP for mobile, automotive, laptop, IoT, AI, VR/AR, and ASIC applications. Main Requirements and Qualifications BS, MS, or PhD degree in Computer Science, Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience. 10+ years of experience in RTL design, microarchitecture, or architecture for complex GPU, graphics, processor, or high‑performance SoC subsystems. Strong hands‑on experience with SystemVerilog, Verilog, VHDL, C/C++, and scripting languages such as Python, Perl, or Tcl. Solid understanding of computer architecture, GPU architecture, SoC architecture, memory hierarchy, interconnects, and performance/power trade‑offs. Proven experience defining or implementing microarchitecture specifications for complex hardware blocks. Experience with performance analysis, bottleneck identification, power optimization, area optimization, and design trade‑off analysis. Strong debugging and root‑cause analysis skills across simulation, emulation, FPGA, and/or silicon environments. Excellent verbal and written communication skills. Strong leadership capability, self‑motivation, ownership mindset, and ability to work effectively in a cross‑functional team environment. Ability to thrive in a dynamic, fast‑paced, and technically challenging engineering environment. Preferred Qualifications Deep knowledge of GPU graphics pipelines, especially geometry processing, tiling, binning, rasterization, pixel processing, shader cores, texture units, memory subsystems, or ray tracing. Hands‑on experience with GPU front‑end or tiler microarchitecture, including one or more of the following areas: Primitive assembly and setup Vertex, tessellation, geometry, or mesh shader pipeline Clipping, culling, and viewport transform Tile binning and primitive‑to‑tile assignment Tile scheduling and load balancing Rasterization and early depth/stencil processing Render backend interaction Cache and memory bandwidth optimization Experience with tile‑based rendering, tile‑based deferred rendering, immediate‑mode rendering, or hybrid GPU rendering architectures. Knowledge of modern graphics APIs such as Vulkan, Direct3D, OpenGL/OpenGL ES, Metal, or OpenCL. Experience with GPU performance modeling, architectural simulation, trace analysis, workload characterization, or graphics benchmark analysis. Familiarity with mobile GPU design constraints, including power efficiency, thermal limits, memory bandwidth optimization, and SoC‑level integration. Experience collaborating with software driver, compiler, performance, verification, and physical design teams. Experience with pre‑silicon validation, post‑silicon bring‑up, silicon debug, performance counter analysis, or hardware profiling tools. Familiarity with AI‑assisted engineering workflows, automation frameworks, or productivity tools for RTL coding, verification, debug, and performance analysis. Salary range: $179,000- $286,000 Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more. MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation. #J-18808-Ljbffr MediaTek Research Lab Inc.