Senior Staff Collateral Design and DFM Engineer

Job Details Job Description: Shape the Future of Semiconductor Innovation at Intel Foundry Organization Overview Manufacturing Development Customer Engineering (MDCE) is Intel's newest organization within Intel Foundry Technology Manufacturing (FTM). We bridge the critical gap between Technology Development (TD) and High-Volume Manufacturing (HVM), advancing technology nodes from initial product qualification to high‑yield production across multiple products while enhancing technologies for our foundry customers. Intel's Chandler, Arizona facility is constructing state-of-the-art fabrication facilities for cutting‑edge technology nodes, including Intel 18A and beyond. Additionally, we're developing legacy technologies with foundry partners to launch HVM operations serving global foundry customers. Position Summary We seek an experienced Senior Staff Collateral Design and DFM Engineer to join our MDCE team and help build a world‑class Foundry Customer Engineering organization. In this role, you will be at the forefront of high‑volume manufacturing (HVM) and ramp leading‑edge advanced logic technologies. You will play a pivotal role in inventing and enhancing Design for Manufacturability (DFM) methodologies that drive measurable improvements in performance, yield, and ramp speed across a broad and dynamic product portfolio. Key Responsibilities Lead cross‑functional teams spanning Process Integration, Device, Yield, Design, OPC/RET, Design Rules, DTP, and CAD to define and continuously enhance DFM rules that accelerate yield improvement and technology ramp on advanced logic nodes Translate silicon learning and yield insights into actionable feedback for design teams, enabling timely updates to layout and DTCO methodologies and flows that catch yield issues earlier in the design cycle Develop, refine, and optimize yield tools and flows within the foundry environment, supporting inline yield detection and continuous process optimization Define and evolve DFM methodologies by deeply understanding silicon process flows, predicting layout and design marginalities, and collaborating with cross‑functional partners to develop robust mitigation rules Drive scribe line layout design and process monitoring structure development to support advanced node characterization and manufacturing readiness Manage design rule development, validation, and waiver processes, ensuring alignment between manufacturing constraints and customer design requirements Serve as the key interface between Process Integration, Yield, Device, and Design teams acting as a trusted technical bridge across all stakeholders Support foundry customers across multiple market segments by developing and implementing tailored DFM solutions that meet diverse application requirements Core Competencies Excellent communication and collaboration skills, with demonstrated ability to engage effectively with design teams, process engineers, and external customers across industry segments Ability to manage multiple concurrent projects and prioritize effectively in a fast‑paced environment Minimum Qualifications Master’s in Electrical Engineering, Physics, or a closely related field 6+ years of experience in DTCO and/or DFM within a semiconductor foundry or advanced technology development environment Experience in DTCO methodologies, including SRAM and Standard Cell design Experience leading cross‑functional teams in defining derivative architectures encompassing design rules, transistors, and interconnects Hands‑on experience in advanced node test chip design and scribe line optimization across 3nm–16nm FinFET or sub‑3nm GAA FET technologies, including Backside Power Delivery (BSPD) Preferred Qualifications Ph.D. in Electrical Engineering, Physics, or a closely related field Experience in scripting and coding for design automation and flow development Experience with physical design flows for yield analysis, DRC, and verification Experience in a foundry environment delivering DFM solutions for varied customer requirements across multiple market segments Experience with the foundry ecosystem, including customer design flows and manufacturing constraints across diverse application domains Why Join MDCE At Intel's MDCE organization, you will work on some of the most advanced semiconductor technologies in the world, with the unique opportunity to shape how those technologies reach high‑volume production. You will collaborate with world‑class engineers, influence foundry strategy, and directly impact Intel's ability to serve the next generation of global customers. Job Type Experienced Hire Shift Shift 1 (United States of America) Primary Location US, California, Santa Clara Additional Locations US, Arizona, Phoenix; US, Oregon, Hillsboro Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $161,550.00 - 317,600.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. * Job posting details (such as work model, location or time type) are subject to change. Additional Information Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. #J-18808-Ljbffr Intel