Cellular ASIC Design Engineer - Protocols

San Francisco Bay Area, California, United States Hardware Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something — you’ll add something. Description We’re looking for a Cellular ASIC Design Engineer, where you will architect and implement protocol processing hardware for next-generation wireless SoCs. You will own the full lifecycle from early architectural exploration and HW/SW partitioning, through RTL implementation, to silicon bring-up and lab validation. You will collaborate closely with software, firmware and verification teams to deliver hardware that balances performance, flexibility, and power efficiency. Responsibilities Micro-architecture and RTL implementation for cellular protocol hardware. Analyze and optimize pipelining architectures to improve performance metrics. Drive latency optimization and quality of service (QoS) support. Define HW/FW/SW partitioning for protocol processing functions. Bring up and debug hardware in the lab. Minimum Qualifications BS and a minimum of 10 years relevant industry experience. Hands‑on expertise in SystemVerilog and Verilog. Skilled in with synthesis and timing analysis tools. Experience with low-power design techniques. Proficiency with AMBA bus protocols (AXI, AHB) or similar on-chip NoCs. Expertise in designing and optimizing scheduling and QoS mechanisms. Preferred Qualifications MS or PhD in Computer Engineering or Electrical Engineering. Understanding of cellular MAC, WiFi MAC or other data‑link layer (L2) protocols. Solid grasp of IP and TCP/UDP protocols. Background in network infrastructure architecture (e.g. routers, access points, switches). Experience with packet buffering, queuing, and scheduling. Knowledge of security algorithms (AES or similar). Experienced with scheduling and arbitration designs for memory subsystems. Developed architectural models in C/C++ or SystemC. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $181,100 and $318,400, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. #J-18808-Ljbffr