Senior Signal Delivery Engineer (Compute Test Division; North Reading, MA)

Opportunity Overview The Innovation Lab is an advanced R&D team that is part of the Semiconductor Test Division at Teradyne. The team is responsible for developing breakthrough concepts for use in Semiconductor Test Systems of the future. A Senior Signal Delivery Engineer will play a critical role ensuring high‑performance signal integrity across advanced semiconductor interfaces, including UCIe-based architectures and microbump interconnects. Lead the design and analysis of high-speed signal delivery systems supporting high-speed industry data interfaces such as PCIe, UCIe, and others. Develop simulation models and perform signal integrity analysis to ensure robust performance across various operating conditions. Collaborate with cross-functional teams including packaging, PCB layout, and silicon design to optimize signal paths and microbump connections. Build and validate prototypes to test signal delivery performance and compliance of system probe card interfaces including microbump and fine pitch probing specifications. Support product development from concept through production, ensuring signal integrity and reliability. Ensure compliance with industry standards and internal quality metrics. Drive PCB design efforts involving very large panels, high layer count sequential builds, and fine pitch sequential lamination. Lead development of ultra-fine pitch MLO (Multi‑Layer Organic) substrates with embedded active and passive components. Coordinate and manage cross‑site, global engineering teams to ensure alignment and execution across time zones. Provide clear, data-driven risk assessments and mitigation strategies to management and stakeholders. Qualifications Bachelor's or Master's degree in Electrical Engineering or a related field. Minimum 7 years of experience in signal integrity or high-speed hardware design. Proven experience with signal delivery in advanced semiconductor systems. Strong working knowledge of interconnect standards. Experience working with microbump technology and its impact on signal integrity. Familiarity with fine pitch probing techniques and associated challenges. Proficiency in simulation tools such as Ansys HFSS, SIwave, ADS, or equivalent. Experience with PCB layout tools and design for signal integrity. Familiarity with lab equipment for signal validation (oscilloscopes, TDR, VNA). Strong analytical and problem‑solving skills. Excellent communication and mentorship abilities. Demonstrated ability to lead and collaborate with global engineering teams. Skilled in presenting technical risk assessments and trade-offs to leadership. Preferred Qualifications Experience in chiplet-based and UCIe system design. Experience in MEMS needle array technology. Experience in cross‑functional hardware development. Only candidates local to the position location are considered; relocation is not available for this position. This position is not eligible for visa sponsorship. Compensation and Benefits Base Salary Range: $166,300 – $266,100 (good faith estimate; varies with experience and skill set). Incentive Plan: Eligible for discretionary bonus(es) based on financial performance. Benefits include medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance, and more. Equal Opportunity Employer LitePoint, a Teradyne Company, is an equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, age, disability status, protected veteran status, or any other characteristic protected by law. We are a VEVRAA Federal Contractor. Current openings may involve access to export-controlled technology and may be subject to export licensing requirements prior to employment. #J-18808-Ljbffr 6AM City, LLC