SoC Architect

An early-stage semiconductor company is seeking a hands-on SoC Architect to help define and deliver a next-generation compute platform for large-scale AI and data-center workloads. This is a highly technical, execution-focused role for an architect who can move from system requirements and architectural tradeoffs to detailed, implementable specifications. You will work across the full SoC lifecycle, partnering closely with design, firmware, validation, packaging, and systems teams to bring complex silicon into production. The role is suited to someone who thrives in ambiguous environments, makes sound decisions under technical and commercial constraints, and remains closely involved through implementation, bring-up, and performance tuning. What You'll Do Define end-to-end SoC and chiplet architectures for high-performance compute platforms. Develop detailed architectural specifications that can be implemented and verified by engineering teams. Architect high-speed host, scale-up, scale-out, and die-to-die connectivity. Define memory-subsystem architecture, including high-bandwidth and low-power memory integration. Model bandwidth, latency, traffic behavior, and system-level performance. Guide memory-controller integration and data-movement architecture. Define control-path architecture, including processor subsystems, boot flows, security, power management, reset, and clocking. Make architecture tradeoffs across performance, power, area, cost, complexity, and schedule. Partner with RTL, firmware, verification, physical design, packaging, and software teams throughout implementation. Develop silicon bring-up, debug, validation, and performance-tuning strategies. Support the transition from architecture through tapeout, first silicon, system integration, and production deployment. Provide technical leadership across multiple engineering disciplines. What We're Looking For Proven experience architecting complex SoCs that reached silicon and shipped in production systems. Strong understanding of major SoC subsystems and the interfaces between them. Experience with high-speed I/O, coherent or non-coherent interconnects, and multi-device communication. Experience with memory-subsystem architecture, bandwidth modeling, and memory-controller integration. Strong knowledge of processor complexes, boot, security, power, reset, and clocking architecture. Ability to translate ambiguous product or system requirements into concrete, verifiable designs. Experience making architectural tradeoffs under performance, power, area, schedule, and cost constraints. Experience working across architecture, RTL, firmware, verification, physical design, packaging, and post-silicon teams. Strong technical communication and specification-writing skills. Comfort remaining hands-on through implementation, debugging, and system bring-up. Preferred Experience Advanced memory technologies and memory-intensive systems. High-bandwidth networking or fabric-attached devices. Early-stage semiconductor or startup environments. Silicon bring-up and post-silicon performance optimization. Hardware-software co-design. SoC Architect, System-on-Chip Architecture, Chiplet Architecture, Multi-Die SoC, AI Accelerator, GPU, Data Center Silicon, High-Performance Computing, PCIe, PCIe Gen6, CXL, UCIe, Scale-Up Interconnect, Scale-Out Interconnect, Die-to-Die, Coherent Interconnect, NoC, Memory Subsystem, HBM, HBM2E, HBM3, HBM3E, LPDDR, DDR, Memory Controller, Bandwidth Modeling, Latency Modeling, Traffic Modeling, Performance Modeling, CPU Complex, Processor Subsystem, Boot Architecture, Secure Boot, Hardware Security, Power Management, Reset Architecture, Clocking Architecture, PPA, Performance Power Area, RTL, SystemVerilog, Firmware, Design Verification, Physical Design, Packaging, 2.5D Packaging, 3D Packaging, Silicon Bring-Up, Post-Silicon Validation, Debug Strategy, Performance Tuning, Tapeout, First Silicon, Hardware-Software Co-Design, SoC Specification, Microarchitecture, System Architecture #J-18808-Ljbffr