Senior ASIC Timing & Physical Design Engineer (Equity)
NVIDIA Corporation
NVIDIA Corporation in Massachusetts seeks a Senior ASIC Timing Design Engineer to drive timing for high-frequency DPUs/SoCs across block to full-chip levels. You will optimize constraints, manage ECO-led timing closure, and push RTL-to-GDS2 through front-end and back-end stages. Ideal candidates have strong STA, ECO, Lean EDA tooling expertise (PrimeTime/Tempus) and scripting with Python, Tcl, and Make. Compensation includes base salary, equity, and benefits. #J-18808-Ljbffr NVIDIA Corporation
Vacancy posted 1 day ago
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