Staff Engineer, Digital Design Engineering

Responsibilities Digital Architecture and Design: Architect and design digital blocks and subsystems of complex high-speed SerDes ICs, including Gigabit-speed serial interfaces and video and data routing solutions. Develop Next-Generation Technologies: Architect, develop, and actively contribute to next‑generation OpenGMSL technologies, including the definition of new architectures and participation in the development of OpenGMSL technical standards for future product generations. Specification Ownership: Write detailed block and subsystem-level specifications for design and implementation. RTL Design and Implementation: Use Verilog and SystemVerilog to design digital blocks, subsystems, and top‑level designs. Verification and Coverage Closure: Develop block‑level testbenches, verify block functionality, and collaborate with verification teams to achieve full‑chip verification and coverage closure. Digital Backend: Perform block‑ and top‑level linting, CDC analysis, and power analysis. Assist with synthesis constraints and timing closure. Mixed‑Signal Integration: Communicate closely with mixed‑signal designers and verification engineers to support mixed‑signal simulations and real‑number modeling across the analog/digital boundary. Documentation and Design Reviews: Prepare technical documentation and lead architecture, design, and peer reviews. Lab Evaluation and Debug: Support silicon bring‑up, characterization, and debug activities. Cross‑Functional Collaboration: Collaborate across analog, digital, verification, test, and product definition teams to define requirements, support production test development, and ensure successful product execution. Technical Leadership: Provide technical leadership for complex SerDes subsystems and products. Minimum Qualifications MSEE or equivalent: Master’s degree in Electrical Engineering or equivalent with 5+ years of relevant experience or PhD with 3+ years of relevant experience. Digital Design: Experience designing and verifying complex digital systems using Verilog/SystemVerilog. System Architecture & Implementation: Demonstrated ability to architect and plan designs at the system level, translating high-level product concepts into robust design implementations. Communication Skills: Clear and concise written and verbal communication skills, with team working experience and a proactive approach to problem‑solving. SerDes & Communications Expertise: Understanding of communication theory, high‑speed SerDes transceiver architectures, and video/data transport. Design Trade‑Offs & Physical Implementation: Solid understanding of digital and analog design trade‑offs, with experience in timing analysis, power estimation, physical design, and DFT concepts. Lab & Silicon Debug Experience: Hands‑on experience with silicon bring‑up and debug. Preferred Qualifications SerDes Standards and Protocols: Expertise in high‑speed SerDes standards and protocols, including Ethernet, USB, PCIe, and/or video (DisplayPort, CSI/DSI, HDMI). Technical Standards Experience: Experience authoring SerDes technical standards and/or participating in industry standards committees. Behavioral Modeling: Experience with behavioral modeling, including verification of mixed‑signal systems with behavioral modeling. Team Leadership: Experience leading teams and/or projects. Benefits Medical, vision and dental coverage. 401k plan. Paid vacation, holidays and sick time. Other benefits. Job Details Job Req Type: Experienced. Required Travel: Yes, 10% of the time. Shift Type: 1st Shift/Days. Expected wage range for a new hire into this position is $134,644 to $201,966. Analog Devices, Inc. is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, or political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law. #J-18808-Ljbffr 1010 Analog Devices Inc.