Director, Custom HBM Design and Architecture

Overview As a Director of Custom HBM Design and Architecture, you will lead a team responsible for the design, integration, and delivery of next‑generation HBM SoC logic die for AI/ML applications. You will drive technical strategy and execution across multiple product generations, working closely with architecture, design, verification, physical design, firmware, and product engineering teams. Key Responsibilities Analyze hardware and software interaction at the system level to identify bottlenecks in existing AI/ML workloads and HBM‑based hardware. Drive future HBM architecture, design, and technology to address bottlenecks, including implementing proof of concept designs. Translate architectural and micro‑architectural specifications into robust, high‑quality RTL implementations across multiple teams. Own RTL design deliverables across the lifecycle, from RTL development through integration, validation, and silicon bring‑up. Drive trade‑offs across performance, power, area, schedule, and risk, ensuring optimal product outcomes. Proactively identify execution risks and implement mitigation strategies across teams and design phases. Build, lead, and scale a high‑performing RTL design and integration team, including recruiting, mentoring, and retention of top engineering talent. Set technical direction and expectations, enabling engineers to execute complex designs with high quality and efficiency. Foster a culture of innovation, accountability, and continuous improvement aligned with organizational values. Develop future technical leaders and strengthen organizational capabilities in HBM SoC design. Qualifications Proven experience leading large‑scale SoC design teams delivering complex SoCs to advanced process nodes (e.g., TSMC). Deep expertise in RTL design, SoC integration, and full RTL‑to‑GDS flows, including synthesis, timing, and sign‑off considerations. Strong experience integrating complex IP subsystems (controllers, NOC, microcontrollers, PHY‑adjacent logic, RAS, MBIST, interfaces). Solid understanding of SoC architecture, clocking, reset, power management, and system‑level design trade‑offs. Experience with pre‑silicon validation, hardware emulation, and post‑silicon debug methodologies. Familiarity with EDA tools and scripting languages (e.g., SystemVerilog, Python, TCL). Knowledge of DRAM/HBM systems and JEDEC standards preferred. Preferred Qualifications 15+ years of relevant SoC design experience with increasing scope and technical leadership. Demonstrated success driving multiple tape‑outs and cross‑functional SoC programs. Strong leadership, communication, and organizational influence skills. Experience building and managing global engineering teams. Compensation US base salary range: $199,000.00 – $379,000.00 a year. Additional compensation may include benefits, bonuses and equity. Benefits Micron offers a choice of medical, dental, and vision plans, income protection programs, paid family leave, paid time‑off, paid holidays, and other benefits. For more details, see the Benefits Guide. Equal Opportunity Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws. #J-18808-Ljbffr Micron Technology, Inc.