Systems Signal Integrity Engineer - Apple Data center

Systems Signal Integrity Engineer - Apple Data Center

Apple is seeking an enthusiastic signal integrity engineer for the system technology team. The candidate will help with concept and feature development, rapid prototyping. The Datacenter organization is looking for an outstanding engineer to support the system-level signal integrity design, analysis and validation aspects of Data center products development. The candidate will work within the System Technology organization to support the system-level Signal Integrity (SI), analysis and validation aspects of data center products development. The candidate should have deep knowledge and familiarity with all aspects of signal Integrity for high speed Serdes, electrical-optical-electrical signaling interfaces deployed in data center products.

The role involves pathfinding studies in silicon development phase where feedback is provided to silicon and packaging team on system integration tradeoffs. And the candidate is expected to work closely with System Design teams to provide detailed SI strategy and guidelines during design execution phase. The candidate is also expected to work with HW Validation teams to develop test-suites to perform system-level validation for evaluation of design margins on the all signal path. The roll includes the SI support through the specific project design process which can include system pathfinding and verification stages, and characterization reviews with continuing guidance through production and ramp.

Minimum Qualifications

• M.S Degree with relevant industry level work experience.
• Familiarity with all aspects of Signal Integrity for high speed SerDes, parallel bus, single ended signaling.
• Familiarity with all aspects of electrical-optical-electrical interface.
• Ability to execute on channel analysis with Signal integrity EDA.
• Measurement expertise with frequency and time domain tools (VNA, TDR) including calibration methods.

Preferred Qualifications

• Ph.D with minimum 3~5 years experience.
• Deep knowledge system level Serdes design and analysis skills. The Serdes knowledge required includes understanding of transmitter and receiver equalization methods (including FFE, CTLE, DFE, VGA gain), CDR behaviors and modeling, link training algorithms and eye margining tool.
• Optical link including MZM modulation, optical cable, PIN, TIA and redriver/retimer.
• Serial bus expertise shall include knowledge of the specifications of PCIe, USB, DisplayPort, HDMI and Thunderbolt. SI skills required include DOE analysis across channel variants, applying equalization and training as required for end-end channel analysis.
• Excellent documentation and communication skills, ability to work independently, a desire to mentor, and demonstrated ability to innovate are required.

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