Senior Design Engineer: SOCs, RTL & Timing Expert
Cadence Inc
Cadence in the United States is seeking an experienced hardware senior engineer to lead a team that designs SOCs and sub-system chips. You will oversee RTL synthesis, floor planning, clock trees, timing closure, IR drop, and physical verification, coordinating Front End RTL and Back End verification teams. Required BS in Electrical Engineering with 7+ years (MS 5+ years or PhD 1+ year). Proficiency with Cadence tools (Innovus, Tempus, QRC, Voltus, Pegasus) and exposure to 5nm/3nm/2nm nodes, #J-18808-Ljbffr
Vacancy posted 2 days ago
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