RTL Design Engineer - AI-SoC & IP Integration
Jobtailor
Jobtailor is seeking an experienced RTL design engineer to contribute to ASIC/SoC development. You will design RTL in Verilog/SystemVerilog, integrate IP blocks, and participate in architectural decisions while ensuring timing, power, and security practices are observed. You will collaborate with verification teams, perform quality checks from RTL through timing convergence, and apply scripting for automation. This role emphasizes design integrity and efficient integration of CPU subsystems. #J-18808-Ljbffr Jobtailor
Vacancy posted 4 days ago
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