Staff/Principal Layout Designer, AI-Optimized Memory

Responsibilities Drive DRAM layout activities for tightly coupled, high-performance memory for AI workloads Apply expert knowledge to deliver high-quality layout designs across analog, mixed-signal, and custom digital domains Drive layout designs for early architecture concepts to demonstrate feasibility and identify optimizationsCollaborate and communicate across domains to ensure successful architecture exploration Requirements Bachelor's or Master's in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience Extensive hands‑on layout experience with critical DRAM blocks and full designs Experience with Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS Solid understanding of layout impacts: speed, capacitance, power, and area Strong understanding of analog layout fundamentals: matching, electro migration, latch‑up, coupling, crosstalk, IR‑drop, and parasitic effects 10+ years of experience in analog and custom layout designs (preferred) Proven layout ability with advanced CMOS processes across technology nodes (e.g., FinFET) Excellent communication and interpersonal skills #J-18808-Ljbffr Jobtailor