Signal Integrity & Power Integrity Engineer

About Majestic Labs We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us! About The Position We are looking for a Senior Signal Integrity (SI) and Power Integrity (PI) Engineer to own end-to-end electrical link performance across our high-speed interconnects - from architecture and pre-silicon modeling through silicon bring-up, validation, and high-volume manufacturing (HVM). This is a hands-on technical role for someone who has taken multiple products from concept to production and knows what breaks (and why) once real volume hits the line. Responsibilities Own signal integrity and power integrity analysis for end-to-end high-speed links, including package, connector, PCB, and cable interconnects Drive SI/PI closure for high-speed SerDes interfaces (112G/224G-class), PCIe (Gen5/Gen6+), and parallel/single-ended interfaces such as DDR/LPDDR memory and chip-to-chip links Perform pre-silicon channel modeling, budgeting, and margin analysis using COM (Channel Operating Margin), IBIS-AMI, and statistical eye methodologies Build and correlate 3D/2.5D EM models (HFSS, PowerSI) against lab measurement (VNA, TDR, BERT, scope) to validate channel and package performance Perform system-level power delivery network (PDN) analysis, decoupling strategy, and power/SI co-design across chip, package, and board Use ADS and MATLAB for circuit-level simulation, link budget analysis, and custom post-processing/automation of simulation and lab data Support silicon bring-up, debug, and characterization in the lab; root-cause SI/PI-related failures and drive corrective actions Partner with ASIC, package, PCB layout, and mechanical teams to define design rules, stackups, routing guidelines, and connector/material selection Lead products through DVT/PVT and into high-volume manufacturing, including establishing test limits, correlating ATE/system-level test data to simulation, and resolving field/yield issues tied to SI/PI margin Contribute to internal methodology, tooling, and design guideline development. Requirements 10+ years of hands-on SI/PI engineering experience in the semiconductor, systems, or networking hardware industry Demonstrated experience across the full product lifecycle - architecture through production and sustained high-volume manufacturing - not just simulation-only roles Deep working knowledge of high-speed SerDes signaling, including 224G (or comparable leading-edge) electrical interfaces, and PCIe link architecture Solid experience with parallel/source-synchronous interfaces such as DDR/memory buses and chip-to-chip interconnects Proficiency with COM-based analysis and IBIS-AMI modeling for channel compliance and margin assessment Strong command of industry-standard tools: Ansys HFSS, Ansys PowerSI (or equivalent 2.5D/3D field solvers), Keysight ADS, and MATLAB Hands-on proficiency with SI/PI lab testing and validation equipment, including Vector Network Analyzers (VNA) for S-parameter extraction, TDR/TDT for impedance and discontinuity characterization, and oscilloscopes for eye diagram, jitter, and signal quality measurement Familiarity with power integrity fundamentals - PDN impedance analysis, decap strategy, DC/AC drop, and chip-package-board co-design Experience working with cross-functional teams (ASIC design, package engineering, PCB layout, test/ATE, manufacturing) to drive designs to closure Excellent written and verbal communication skills; able to clearly present technical risk and trade-offs to both engineering and program stakeholders Preferred Qualifications Experience with additional high-speed standards (CXL, Ethernet SerDes) Scripting/automation experience (Python) for simulation flow automation or data analysis Experience with connector, cable, or optical module electrical characterization Familiarity with signal/power co-simulation and chip-package-system (CPS) modeling flows Exposure to compliance testing and industry standards bodies (PCI-SIG, OIF-CEI, JEDEC) At Majestic Labs, we are shaping the next paradigm and making AI ubiquitous by building radically better infrastructure across the entire stack—from systems engineering and VLSI to compilers and AI applications. This epic mission requires a relentless culture of innovation, grit, and dedication. Our employees are our most important asset. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. #J-18808-Ljbffr Majestic Labs ai