Principal Embedded Firmware Engineer AI/HPC Networking Silicon

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Principal Embedded Firmware Engineer — AI/HPC Networking Silicon based in the United States.
As a Principal Embedded Firmware Engineer, you will shape the firmware architecture powering next-generation networking silicon for AI and high-performance computing (HPC) infrastructure. You will lead the development of bare-metal firmware responsible for securely booting, provisioning, and supervising on-chip acceleration engines across complex, multi-die systems. Your work will establish the reliable infrastructure required to support demanding compute workloads at scale. Collaborating closely with ASIC, RTL, and software engineering teams, you will define hardware/software interfaces, strengthen security, and improve system bring-up and validation. You will combine hands-on engineering with technical leadership, architectural decision-making, code reviews, and mentorship. This fully remote opportunity is suited to an experienced firmware architect who enjoys tackling low-level silicon challenges and using AI-assisted engineering tools to accelerate development while maintaining rigorous quality standards.
Accountabilities You will own key elements of the embedded firmware architecture, ensuring that management firmware securely provisions, initializes, monitors, and updates on-chip acceleration engines. You will also establish engineering standards and guide technical execution across the platform.

• Firmware Architecture and Development: Architect, design, and implement bare-metal C firmware running on a RISC-V management core to provision, boot, and supervise arrays of on-chip acceleration engines.
• Secure Firmware Loading: Develop and maintain the secure firmware-loading pipeline, including fetching images from flash, coordinating authentication through hardware root-of-trust mechanisms, and distributing verified images into individual engines local memories using on-chip fan-out and DMA hardware.
• Engine Initialization and Health Monitoring: Implement per-engine bring-up, reset sequencing, and health validation through control and status registers, with robust timeout handling, error recovery, and enforced security invariants.
• Multi-Engine and Multi-Die Support: Scale firmware distribution and initialization across numerous engines and multiple dies, supporting runtime rebooting and in-field firmware updates.
• Hardware/Software Interface Definition: Define and maintain hardware/software contracts with ASIC and RTL teams using a datamodel-first workflow and tools such as SystemRDL, Kaitai, and YAML-based code generation.
• Firmware Validation and Testing: Validate firmware using functional simulators such as QEMU, supported by automated unit and integration tests.
• AI-Assisted Engineering: Integrate AI tools into firmware design, implementation, debugging, and testing workflows while ensuring generated code and recommendations are rigorously reviewed and validated.
• Technical Leadership: Establish architecture and coding standards, lead design and code reviews, make key technical decisions, and mentor engineers across the team.
• Cross-Functional Collaboration: Work closely with silicon, hardware, and software engineering teams to resolve integration challenges and deliver secure, reliable, production-ready firmware.