Electrical Design Engineer (Compute Test, Arden Hills, MN)

Electrical Design Engineer (Compute Test, Arden Hills, MN)Date: Nov 6, 2026Location: Arden Hills, MN, USCompany: TeradyneOur Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their unique strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better choices, drives innovation and delivers better business results.Opportunity Overview Teradyne's Semiconductor Test Division is seeking a Hardware Engineer – Signal Integrity to join the Digital Instrument hardware team in Arden Hills, Minnesota. Our digital instruments test the world's most advanced semiconductor devices, with signals spanning an unusually wide spectrum: from kHz-rate control buses to tens-of-GHz serial links. In this role, you will own signal integrity (SI) and power integrity (PI) for printed circuit board assemblies (PCBAs) in our digital instruments, from pre-layout modeling and simulation through lab correlation and production release, and design selected functional circuit blocks. You will work closely with Hardware, Firmware, Software, Mechanical, and Test engineers to turn instrument requirements into design guidelines and constraints, catch SI/PI risks before they become board re-spins, and solve problems on new and existing designs.Conduct signal integrity and power integrity (SI/PI) simulation and evaluationOwn pre- and post-layout SI simulation for interfaces including I2C/SPI/JTAG, DDR, Ethernet, PCIe Gen 1–7 (up to 128 GT/s), and proprietary links, covering NRZ and PAM4 channel loss budgets, crosstalk, jitter/eye, impedance, and connector, via, and BGA breakout optimizationExecute power integrity evaluation, including power distribution network (PDN) impedance, IR drop, and decoupling selectionModel and correlate the full tester-to-DUT signal path (instrument, interconnect, DIB/loadboard, socket) against VNA, TDR, and BERT/sampling-scope measurementsAll About You We seek individuals who share our passion and dedication. Our commitment to customer success drives us to go the extra mile. If you're ready to join us in this mission, take a closer look at the minimum criteria for the position.Education and Experience Bachelor of Science (BS) in Electrical Engineering or related field with minimum 5 years of relevant design, simulation, and model creation experience in a product development environment OR Master of Science (MS) in Electrical Engineering or related field with minimum 3 years of relevant design, simulation, and model creation experience in a product development environment Relevant experience should include SI/PI simulation and model creation, PCB stack-up and layout review, schematic capture and review, and electronic lab correlation measurementKnowledge / Technical Requirements Strong working knowledge of signal integrity and power integrity for low-speed through multi-gigabit interfaces Strong proficiency with SI/PI and circuit simulation tools and scripting (e.g. Cadence Sigrity/Clarity 3D, Ansys SIwave/HFSS, SPICE, Python) Hands-on experience with high-speed channel analysis, including S-parameters, IBIS models, and jitter/eye analysis Experience with schematic and layout CAD packages (e.g. Cadence Allegro/OrCAD, Altium, Siemens Xpedition) Working knowledge of board-level circuit design (e.g. clocking, termination, power sequencing) and schematic reviewSkills and Abilities Proven proficiency with high-speed lab measurement equipment (e.g. VNA, TDR/TDT, sampling oscilloscopes, BERT) Excellent verbal, written, and presentation communication skills, including with geographically dispersed teams Proven ability to work on your own and collaborate effectively in team environmentsPreferred Qualifications 2D/3D model extraction and Gerber/ODB++ artwork review PAM4 channel analysis and S-parameter de-embedding Board-level digital and mixed-signal circuit design, including FPGA-based designs, clocking, and ADC/DAC Familiarity with relevant industry standards (e.g. IPC, JEDEC) ATE, DIB/loadboard, or probe-card SI experienceWe are only considering candidates local to position location and are unable to provide relocation for this position. This position is not eligible for visa sponsorship. Compensation: The base salary range for this role is $114,000 – 182,500. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location. Benefits: Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details.