Signal Integrity Engineer

This role has been designed as “Onsite” with an expectation that you will primarily work from an HPE office. Job Title Engineering Job Level

TCP_05

Salary The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level. – United States of America: Annual Salary USD 174,000 - 352,500 in California The listed salary range reflects base salary. Variable incentives may also be offered. Key Responsibilities Perform COM (channel margin analysis) to provide design trade-offs amongst ASIC package, board, and connectors. Develop ASIC PAM4 SerDes channel simulation models and correlate to test structures. Correlate ASIC PAM4 SerDes simulation results with measurements and work with component and ASIC vendors to improve model accuracy. Perform PCB timing analysis, work with board engineers and layout designers to implement all design SI rules, develop and document all layout/SI design rules and checklists. ASIC PAM4 SerDes parametric tuning to improve design margins of serial links. Perform SI DVT measurements on boards and correlate simulations with DVT measurements. Provide technical assessment of projects to SI management team. Basic Requirements Typically, 10+ years of Signal Integrity analysis experience with a bachelor’s degree in Electrical engineering, Computer engineering, Microwave, and/or RF engineering. Typically, 8+ years of Signal Integrity analysis experience with a master’s degree in Electrical engineering, Computer engineering, Microwave, and/or RF engineering. Experience with 56G/112G ASIC PAM4 SerDes technologies is required. 200G ASIC PAM4 experience desired. Hands‑on experience in serial channels up to 200G line rates for coefficient tuning, TP1A measurements. Preferred Skills Proficient with CAD tools such as Ansys HFSS, SIwave ADS, Allegro, Sigrity and MATLAB. Proficient with lab equipment such as oscilloscopes, Vector Network Analyzers, Time Domain Reflectometers, Spectrum Analyzers, phase noise Analyzers. Good lab debug skills a plus. Strong capabilities to debug and provide solutions for ASIC PAM4 SerDes and channel performance issues. Design implementation for system clocks and solid understanding of PLL design and debug. PCB Stack‑up design using 2‑d field solvers. Knowledge and Skills Good oral and written communication skills. Team player able to collaborate with people across geography and in a matrix organization. Capable of working on several projects simultaneously. Benefits Health & Wellbeing: We strive to provide our team members and their loved ones with a comprehensive suite of benefits that support their physical, financial, and emotional wellbeing. Personal & Professional Development: We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division. Unconditional Inclusion: We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories. #J-18808-Ljbffr Hewlett Packard Enterprise