Hardware Engineer IV

Hardware Engineer IV Sunnyvale CA 12 Months Job Description: Role Summary:We are seeking an experienced EE Validation Engineer to support hardware validation of next-generation smart glasses, working closely with the validation lead.In this role, your primary focus will be monitoring validation progress, reviewing CM test reports, analyzing failures, and coordinating with EE design partners to drive issues to closure.You will also guide CM engineers on measurement procedures and perform hands-on PI/SI debug when needed.While you must possess strong hands-on measurement skills, the majority of your time will be spent interpreting data, tracking issues, and ensuring problems are resolved efficiently.You will not own final validation decisions, but you are expected to be technically strong enough to flag risks, recommend actions, and keep execution on track under the lead's direction.Must-Have Skills4+ years of EE hardware validation experience with strong emphasis on power integrity and signal integrityAbility to develop test procedures that others execute — clear technical writing, structured SOPs, annotated diagrams. Strong schematic reading skills — trace signal paths, understand power distribution, map circuit function from schematics and datasheetsPCB layout review experience — assess probe access, SI/PI risk, debug strategy. Expert-level knowledge of lab instruments: high-bandwidth oscilloscopes, power rail probes, active/differential probes, current probes, spectrum analyzersNice-to-have SkillsExperience with wearable, mobile, or IoT hardware (space-constrained, low-power designs)Familiarity with proto/EVT/DVT/PVT build cycles and NPI environmentsExperience with issue tracking systems and cross-functional coordination in hardware programsResponsibilities:Issue Tracking & Closure (Primary Focus ~60%)Review CM-generated validation reports: verify data quality, flag anomalies, confirm pass/fail criteria are correctly appliedAnalyze validation failures; determine whether issues are measurement errors, design defects, or assembly quality problemsCoordinate with EE design partners to present data, propose root cause hypotheses, and support corrective action decisionsTrack open issues through resolution; ensure fixes are validated and closed in a timely mannerFacilitate communication between CM, EE design, layout, and firmware teams to keep issues movingMaintain issue tracker and provide regular status updates to the FTE validation leadMonitor overall validation progress against milestones; escalate risks and blockers earlyCM Guidance (~20%)Develop clear, repeatable test procedures (SOPs) that CM technicians can execute independentlyTrain and guide CM engineers/technicians on proper measurement techniques, probe placement, fixture usage, and data collectionDefine probe points and measurement access strategy; communicate to CM with annotated layout markupsProvide real-time technical guidance to CM when measurements yield unexpected resultsEstablish clear acceptance criteria and escalation paths for CM to follow, in alignment with the FTE validation leadHands-On Measurement & Debug (~20%)Perform PI/SI measurements that require senior-level judgment (e.g., first article bring-up, intermittent failures, subtle noise sources)Validate CM measurement setups by performing correlation measurementsDebug escalated issues that CM cannot resolve independentlyDevelop new measurement methodologies and fixtures for novel circuits or challenging probe accessSupport prototype bring-up and characterization during build phasesTechnical Knowledge Required:Power Integrity (PI)DC-DC converter characterization: line/load regulation, efficiency, transient response, output ripple/noisePower sequencing validation and timing verification against IC specificationsPower rail stability under varying load conditions; current profilingBattery charging circuit validation: charge profiles, protection, thermal limitsPDN concepts: ground bounce, decoupling strategy, voltage droop analysisSignal Integrity (SI)High-speed interface measurement: MIPI CSI, SPI, I2C, I2S/PDM, USB, UARTSignal quality assessment: rise/fall times, overshoot/undershoot, ringing, eye diagramsCrosstalk, reflections, and impedance discontinuities on flex/rigid-flex assembliesClock signal quality and jitter characterizationProtocol-level correlation with physical-layer signal issuesSchematic & Layout CompetencyRead and interpret multi-page schematics to understand circuit topology, power trees, and signal routingReview PCB layout (rigid and flex) to identify optimal probe locations and debug access pointsAssess layout for SI/PI risk: trace routing, return path continuity, impedance control, via transitionsProvide layout feedback to design team for improved testabilityRequired Qualifications:BS/MS in Electrical Engineering4+ years of EE hardware validation experience with strong emphasis on power integrity and signal integrityProven ability to analyze test data, identify root causes, and drive issues to closure with cross-functional teamsExperience reviewing test reports for correctness, identifying gaps, and driving follow-up actionsAbility to develop test procedures that others execute — clear technical writing, structured SOPs, annotated diagramsStrong schematic reading skills — trace signal paths, understand power distribution, map circuit function from schematics and datasheetsPCB layout review experience — assess probe access, SI/PI risk, debug strategyExpert-level knowledge of lab instruments: high-bandwidth oscilloscopes, power rail probes, active/differential probes, current probes, spectrum analyzersExperience with DC-DC converter characterization and high-speed digital signal measurementsSolid understanding of transmission line theory, impedance matching, and flex PCB signal integrity challengesStrong communication skills — ability to explain complex EE issues clearly to CM teams and design partnersPreferred Qualifications:Experience working with CMs or ODMs in a validation support capacityExperience with wearable, mobile, or IoT hardware (space-constrained, low-power designs)Familiarity with RF measurement (BLE/WiFi TX power, sensitivity, antenna return loss)Familiarity with proto/EVT/DVT/PVT build cycles and NPI environmentsExperience with issue tracking systems and cross-functional coordination in hardware programsTools & Environment:Keysight/Tektronix oscilloscopes (≥1 GHz), power rail probes, active probes, SMUs, VNAs, protocol analyzersscripting, schematic/layout viewers (Allegro, Altium, or equivalent), data analysis toolsGoogle Workspace, Tasks/JIRA for issue trackingDaily interaction with validation lead, CM engineers (remote and on-site), EE design team, and FWStory Behind the Need – Business Group & Key ProjectsSurrounding team & key projectsApart of the wearables, smart glasses team. Focus on tracking validation progress, reviewing test reports, analyzing failures, and coordinating with EE design partners to resolve issues. You'll guide CM engineers on measurement procedures and perform hands-on PI/SI debug as needed. The emphasis is on data interpretation, issue tracking, and driving resolution—not on owning final validation decisions. You're expected to flag risks, recommend actions, and keep execution on track under the lead's direction.How many rounds of interviews? 2Types of Interviews: TechnicalInterview Duration: 45 mins Applicant Notices & DisclaimersFor information on benefits, equal opportunity employment, and location-specific applicant notices, click here