SoC Physical Design Engineer, STA/Timing
$139.5k - $258.1kApple Inc.
SoC Physical Design Engineer, STA/Timing Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it! Join us to help deliver the next groundbreaking Apple product.In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology. Description Work with design teams to understand and debug constraints and facilitate logic changes to improve timing. Work with the Physical Design team, highlighting issues and best practices. Help create timing ECO’s for project tapeout. Create and maintain scripts and methodologies for analysis and runs. Create documentation and help with guidelines/specs. Deep analysis of timing paths to identify key issues. Implement timing infrastructure. Minimum Qualifications Minimum BS and 3+ years of relevant industry experience. Experience with large design STA and Timing Closure. Programming skills with Perl and TCL. Preferred Qualifications Hands‑on experience in STA. Familiar with important aspects of timing of large high‑performance SoC designs in sub‑micron technologies. Proficient in STA and methodologies for timing closure and have a fundamental understanding of noise, crosstalk, and OCV effects, among others. Familiar with circuit modeling, including SPICE models, and worst‑case corner selection. Familiar with ECO techniques and implementation. Good communicator who can accurately describe issues and follow them through to completion. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $139,500 and $258,100, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. Apple accepts applications to this posting on an ongoing basis. #J-18808-Ljbffr Apple Inc.
$140k - $210k
Qualcomm is seeking skilled engineers to join its SoC Implementation Team in San Diego, California, focusing on timing constraints development, power analysis, and static timing analysis for premium-tier chips. The ideal candidate will have a relevant degree and at least...Suggested$115.6k - $173.4k
...Technologies, Inc. Job Area: Engineering Group, Engineering... ...skilled and motivated Physical Design Engineer to join our... ...‑and‑route, DRC and timing closure. This role involves... ...timing analysis (STA) tools (e.g., PrimeTime... ...and document IP (block/SoC) development for a...SuggestedFull timeWork experience placementImmediate startWork from homeShift work$220k
Principal SoC Full-Chip Implementation Physical Design & Verification Engineer job at Acara Solutions. San Diego, CA. Acara Solutions has been providing advanced manufacturing... ...bump design, Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification....Suggested$45k - $121k
Physical Design Engineer (PnR / PPA / Timing Closure) Job Title: Physical Design Engineer (PnR / PPA / Timing Closure) City: Mountain View | State/Province... .... Develop and maintain timing constraints (SDC) and STA signoff methodologies. Perform EMIR (Electromigration...SuggestedMinimum wageLocal area$139.5k - $258.1k
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Encore Semi Llc in San Diego is seeking a talented Physical Design Engineer with an Active Secret Clearance to join its Advanced Microelectronics... ...critical in designing and implementing high-performance ASICs and SoCs for national security applications. The ideal candidate...$211.9k - $317.9k
...’re looking for a CPU Physical Design expert to push the limits... ...design quality Drive timing, power, and area... ...advanced nodes Mentor junior engineers and help raise the... ...of experience in ASIC/SoC Physical Design Strong... ...synthesis, place & route, STA, signoff) Experience...Work experience placementWork from homeWorldwide- ## Job Description# Physical Design Engineer* The client is developing next-generation silicon to power... ...closure of complex, high-performance SoCs used in advanced wireless and RF... ...Perform and resolve congestion analysis, timing closure, and physical optimization.* Execute...
- Physical Design Methodology CAD Engineer Do you love creating elegant solutions to highly complex challenges?... ...efficient processor, system-on-chip (SoC). You’ll ensure Apple products and... ..., RC extraction, IR and static timing analysis (STA). Working directly with EDA tool...Relocation
- Qualcomm is seeking a CPU Physical Design expert to drive the next generation of computing in San Diego. In this key role, you will own critical... ...design strategies. The position demands over 10 years of ASIC/SoC experience and expertise with RTL-to-GDSII processes. Enjoy...
$120.3k - $210.1k
...development team. Our wireless SoC organization is responsible... ...emphasizing highly energy-efficient design and new technologies that... ...world-class vertically integrated engineering team spanning RF/Analog... ...areas, and thrive during crisis times, we encourage you to apply. Description...Relocation$134.8k - $245.8k
...solutions? As part of our Digital Design Engineering group, you’ll take... ...Library Characterization (Timing/Power/Variation/etc) for all... .... Engage with CPU, SOC and GPU teams on physical design requirements. Minimum... ...or Static Timing Analysis (STA) is a plus. Knowledge of...Relocation$171.6k - $302.2k
...development team. Our wireless SOC organization is... ...highly energy efficient design and new technologies... ...vertically integrated engineering team, spanning RF/Analog... ...design Synthesis and timing constraints Power analysis... ...end flows - Lint, CDC, STA, LEC Knowledge and...Relocation$127.2k - $190.8k
...Qualcomm Technologies, Inc. - Engineering Group, DSP Architecture and Design. A variety of high... ...Qualcomm’s multi-tier mobile SOC, Server IoT, Automotive... ...design, synthesis, static timing analysis, PLDRC, clock... ...power intent etc Work with physical design team on design...Work experience placement$171.6k - $302.2k
...a world‑class silicon design team which delivered an... ...and your team will apply engineering fundamentals and start... ...influence CPU / GPU / SoC / Neural Engine / Camera... ...optimizing for power, timing, area and yield. Schematic... ...of nanometer device physics, leakage mechanisms, technology...Work experience placementRelocation- ## Senior ASIC Design Engineer - TerawaveApplylocations: San Diego, CA: Central... ....We are seeking a ASIC/SOC Design Validation engineers (... ...(phy and MAC)* Sequenced and time bound data movement in DSP structures... ...drug testing as well as DOT physical**Benefits*** Benefits include...Permanent employmentTemporary workLocal areaWorldwideNight shift
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As part of our Silicon Engineering group, you will take imaginative and... ...world. Join us, and you will help design products that bring to our... ...for Validation Engineers. The SoC hardware development team is looking... ...engineer to fill a full‑time position. The primary role is...Full timeRelocation$180.4k - $270.6k
...Technologies, Inc. Job Area Engineering Group, Engineering... ...> DSP Architecture and Design General Summary A variety... ...’s multi-tier mobile SOC, IoT, Automotive roadmap... ..., synthesis, static timing analysis, formal verification... ..., etc. Work with physical design team on design constrain...Work experience placementWork from home- A leading technology firm in San Diego seeks a Physical Design Methodology CAD Engineer to tackle complex physical design challenges and develop innovative solutions. The ideal candidate will have experience with CAD tools and relevant scripting languages, along with a...
$134.8k - $245.8k
...importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next‑generation, high‑performance, power‑efficient processor, system‑on‑chip (SoC). Joining this group means you’ll be responsible for crafting and building the...Relocation$120.3k - $210.1k
Wireless PHY Design Verification Engineer Join Apple's Wireless Connectivity team developing state-of-the-art WiFi SoCs that power hundreds of millions of Apple products worldwide. You'... ...Verification Engineer, you'll ensure first-time-right silicon success through...WorldwideRelocation$171.6k - $302.2k
...solutions? As part of our Silicon Engineering group, you will generate... ...of the team responsible for designing state-of-the-art ASICs that are... ...generations of Apple SOCs. This role provides an opportunity... ...mechanisms. Familiarity with physical design tools for power optimization...Relocation$128k - $192k
...Technologies, Inc. Job Area: Engineering Group, Engineering Group > Modem... ...skilled Modem Hardware Design Verification Engineer to join... ...design teams to ensure first‑time‑right silicon for high‑performance... ...Knowledge of 4G/5G 3GPP physical layer standards is a strong plus...Work experience placement$171.6k - $302.2k
Description We're looking for a Cellular ASIC Design Engineer, where you will architect and implement... ...hardware for next-generation wireless SoCs. You will own the full lifecycle from... ...Verilog. Skilled in with synthesis and timing analysis tools. Experience with low‑power...Relocation$192.05k - $268.87k
...satellite communications network designed to deliver symmetrical data... ...are seeking an RFIC Design Engineer to design and develop advanced... ...least 20 hours/week) Paid Time Off: Up to four (4) weeks per... ...drug testing as well as DOT physical Equal Employment Opportunity...Permanent employmentTemporary workLocal areaWorldwide$140k - $170k
Johnson Service Group is seeking a Design Engineer III for a temp to perm position located in San... ...and innovative problem solver. Physical Requirements Specific vision abilities,... ...tasks may be assigned to the employee from time to time; or The scope of the job may change...Weekly payPermanent employmentTemporary workFor subcontractor$127.2k - $190.8k
A leading technology company in San Diego is seeking an ASIC design engineer with strong RTL development skills. The role involves developing RTL for micro-architecture and collaborating closely with verification and design teams. Minimum qualifications include a Bachelor...$122.5k - $183.7k
...Technologies, Inc. Job Area: Engineering Group, Camera Engineering General... ...is looking for a strong ASIC design engineer for an exciting... ...Crossing checks, synthesis, timing analysis, and low power checks... ...Experience working with synthesis and physical design teams TCL/Perl/Python...Work experience placementWork from home$171.6k - $302.2k
...wireless RFIC team architects, designs, and validates radio... ...integrated into complex wireless SoCs. Our wireless organization is... ...-class vertically integrated engineering team spanning RF/Analog architecture... ...IC level. Familiarity with timing analysis tools (Nanotime,...Relocation
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