FPGA Engineer

Worker Type Regular Job Description AV is seeking skilled and adaptable FPGA engineers to work as members of a multi-disciplinary team supporting multiple technology areas. Our Space Tech division develops high-performance electromechanical, electro-optical, control, and communication systems. These solutions include digital signal processing algorithms deployed using System on Chip (SoC) or Field Programmable Gate Arrays (FPGAs) in combination with General Purpose Processors (GPPs) and microcontrollers. Responsibilities Develop and maintain general-purpose and mission specific RTL/Firmware Develop and maintain firmware for peripheral interfaces Analog to Digital Converters Digital to Analog Converters Serial links and communication interfaces (SpaceWire, SPI, CameraLink, 1Gb+ Ethernet, MIL-1553B) Develop and maintain automated FPGA firmware platform build scripts Deploy firmware to physical devices Architect and develop firmware for space electronics, including FPGAs, microcontrollers, and RTOS-based systems. Optimize embedded software for radiation-hardened and high-reliability environments. Conduct system integration, testing, and validation of firmware in simulated and real-world aerospace conditions. Support compliance with space industry standards (NASA, ESA, MIL-STD). Required Qualifications Bachelor's degree in electrical engineering, computer engineering, or computer science. 2-3 years of professional experience designing using hardware description languages (VHDL or Verilog) Experience deploying firmware to physical devices Experience in conducting system integration, testing, and validation of firmware in simulated and real-world conditions. Ability to obtain and maintain a US security clearance. Preferred Qualifications Some experience using Xilinx devices (Zynq, Virtex / Kintex) and toolchains (Vivado / ISE) and/or Microchip devices (RTAX / ProASIC / RTG4) and toolchains (Libero). Some experience doing firmware development in embedded systems, preferably for aerospace or space applications. Knowledge of serial communication protocols and standards. Familiarity with multiple clock-domain digital design techniques. Familiarity with in-system debuggers and logic analyzers. Familiarity with designing and managing FPGA physical constraints. Familiarity with Tool Command Language (TCL). Proven, demonstrated experience taking VHDL or Verilog designs to a hardware environment. Familiarity with the Xilinx SoC devices. Familiarity with FPGA floor planning techniques. Familiarity with Xilinx System Generator. Familiarity with other computing languages (C/C++, Python, Java). Familiarity with verification techniques, including linting and constrained random testing. Knowledge of RTOS, bare-metal firmware, and hardware-software co-design. Experience working with hardware accelerators and space communication protocols. Familiarity with other synthesis and simulation environments (Synopsys, Aldec). ITAR Requirement This position requires access to information that is subject to compliance with the International Traffic Arms Regulations ("ITAR") and/or the Export Administration Regulations ("EAR"). In order to comply with the requirements of the ITAR and/or the EAR, applicants will be asked to provide specific documentation to verify U.S. person status under the ITAR and the EAR. A "U.S. person" according to their definition is a U.S. citizen, U.S. lawful permanent resident (green card holder), or protected individual such as a refugee, or asylee. See 22 CFR. 120.15. Some positions will require current U.S. Citizenship due to contract requirements. Benefits AV offers an excellent benefits package including medical, dental, vision, 401K with company matching, a 9/80 work schedule and a paid holiday shutdown. For more information about our company benefit offerings please visit: EEO Statement We are proud to be an EEO/AA Equal Opportunity Employer, including disability/veterans. AeroVironment, Inc. is an Equal Employment Opportunity (EEO) employer and welcomes all qualified applicants. Qualified applicants will receive fair and impartial consideration without regard to race, sex, color, religion, national origin, age, disability, protected veteran status, genetic data, sexual orientation, gender identity or other legally protected status. #J-18808-Ljbffr AV