ASIC & FPGA Design Engineer Stf - E4

Requisition ID: 9699ERP Eligible?: YesERP amount: $50 LMRecognitionRelocation: PossibleType: ExemptShift: 1Clearance Prior to Start: NoneFinal Clearance: TS/SCIPay Transparency: $135,700.00 - $251,900.00Experience Level: Experienced ProfessionalFT/PT/Casual: FullTimeDepartment: SpaceBusiness Unit: SpaceStandard Job DescriptionLockheed Martin Space is seeking a Field Programmable Gate Array (FPGA) Design Engineer to work on space-based mission processing capabilities at the edge. This position will help our team evolve ground-based mission processing applications of remote sensing payloads onto flight hardware for onboard mission processing operations. In this role, the FPGA Design Engineer will be responsible for leveraging the Vivado Design Suite and hardware design languages VHDL and Verilog to deploy processing code and algorithms onto flight hardware. This position will work alongside research scientists, software engineers, and other FPGA engineers on the APEX (Advanced Programs and Exploitation) team.The selected candidate will be expected to:develop an understanding of mission processing code written in C++ and implement for hardware processing.develop, integrate, and test of processor subsystem features and interfaces in FPGA hardware.generate requirements, create FPGA code, and test bench development.Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information.This position is in beautiful Boulder, Colorado at our offices which have a collaborative and modern agile workspace.Basic QualificationsBachelor of Science or higher from an accredited college in Electrical Engineering, Computer Engineering or related discipline, or equivalent experience/combined education.Ability to obtain a TS/SCI Clearance required for this role.Understanding of HDL Languages (VHDL & Verilog)Experience designing with VivadoDesired SkillsProficient in Matlab & C++Digital logic design experience.Experience interfacing FPGAs with processors.Experience with Vitis Model Composer.Experience with Matlab HDL CoderFamiliarity with Xilinx platforms and tools.Knowledge of FPGA concepts like clock domains, memory hierarchies, and routing.Demonstrated experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test).Knowledge of space-grade/qualified FPGAs and ASICs.Pay InformationFull-Time Salary Range: $135700.00 - $251900.00At Lockheed Martin, we know mission success starts with taking care of our people. Our Total Rewards program is designed to attract top talent, support your well-being, and help you grow—both professionally and personally.The salary range for this position is as listed on the requisition. Please note that the salary information listed is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market(work location) and business considerations when extending an offer. Benefits offered: Medical, Dental, Vision, Flexible work arrangements and schedules (e.g., 4x10), 401(k) match, Paid time off, Holidays, Parental Leave, EAP, Flexible Spending Accounts, Education Assistance, Life Insurance, Short-Term Disability, and Long-Term Disability.Annual short-term and/or long-term incentive compensation programs may be offered depending on the position. Payments under these annual programs are not guaranteed and can vary from year to year and are tied to a range of performance metrics.For (Washington state applicants only) Non-represented full-time employees: accrue at least 10 hours per month of Paid Time Off (PTO) to be used for incidental absences and other reasons; receive at least 90 hours for holidays. Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year.