Senior Design Verification Engineer

Senior Design Verification Engineer

Location: 810 West Hwy 71, Marble Falls, TX Employment Type: Temp to Perm Work Location: Marble Falls, TX Work Schedule: Full-time (Day Shift) Interview Type: 1 Round – Virtual Interview

Job Summary

The Senior Design Verification Engineer is responsible for verifying and validating complex digital and/or mixed-signal designs to ensure functionality, performance, and compliance with specifications. This role involves developing verification strategies, creating test plans, executing simulations, debugging design issues, and collaborating closely with design, architecture, and cross-functional teams to deliver high-quality silicon or system-level solutions.

Essential Functions Of The Role

Verification Planning & Execution

• Lead end-to-end design verification activities, including verification strategy definition, test plan creation, and execution.
• Develop and maintain robust verification environments using industry-standard methodologies.
• Ensure designs meet functional, performance, and reliability requirements.

Testbench Development

• Design and implement scalable, reusable verification testbenches using SystemVerilog/UVM or equivalent frameworks.
• Create directed and constrained-random tests to achieve thorough functional coverage.

Debugging & Issue Resolution

• Identify, analyze, and debug functional and performance issues at block and system levels.
• Work closely with design engineers to resolve bugs and verify fixes.

Coverage & Quality Metrics

• Define and track functional, code, and assertion coverage metrics.
• Ensure verification closure based on coverage goals and quality standards.

Cross-Functional Collaboration

• Collaborate with RTL designers, architects, firmware, and validation teams to ensure design intent is accurately verified.
• Participate in design reviews and provide verification feedback early in the development cycle.

Documentation & Reporting

• Prepare and maintain verification plans, test cases, coverage reports, and verification sign-off documentation.
• Communicate verification status, risks, and progress to technical leads and stakeholders.

Mentorship & Leadership

• Mentor junior verification engineers and promote best practices in verification methodology.
• Contribute to continuous improvement of verification processes and tools.

Key Success Factors

• Strong expertise in digital design verification methodologies (UVM, SystemVerilog).
• Experience verifying complex SoC, ASIC, or FPGA designs.
• Solid understanding of digital design concepts, RTL (Verilog/VHDL), and simulation tools.
• Proven ability to debug complex design issues efficiently.
• Strong analytical, problem-solving, and decision-making skills.
• Experience with coverage-driven verification and regression management.
• Proficiency in verification tools, simulators, and scripting (Python, Perl, or TCL preferred).
• Excellent communication and collaboration skills.
• Ability to work independently and lead verification efforts in a fast-paced environment.
• Commitment to continuous learning and adoption of verification best practices.