US_East | Network Design Engineer_L3

Analog/Mixed-Signal Dv Engineer

Analog/Mixed-Signal Design Verification

Location: Remote

Analog/Mixed-Signal Design Verification

• Extract modeling specifications from designers

• Development of Analog/Mixed-Signal model in System-Verilog

• Development of UVM Testbench and developing test cases

• Run simulation and fix the behavioral model working with Circuit designer.

• Develop timing model for the circuit working with layout engineer.

• This role will provide the ability to directly influence design related changes as required to meet functional specifications

• Determine whether anomalous symptoms are caused by errors in the specifications, models, testbench, or design

• Support integration of composite models into larger composite models maintained by other groups

• Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc

• Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog-A code to control analog circuits (e.g band-gap, PLL, Amplifier, Filters)

• Familiarity with behavioral Verilog code for an analog circuit

• Ability to write thorough test benches for digital and AMS simulators

• Deep understanding of constraints, especially for mixed-signal designs, including multiple clock domains and clock gating

• Familiarity with timing closure and static timing analysis tools

• Experience with scan chain vector generation and verification