Senior Layout Designer (Analog/Mixed Signal)

Mandatory Requirement: 10+ years of industry experience in analog/mixed-signal layout design in advanced process nodes (2nm–16nm, preferably TSMC). Proven track record designing layouts for high-speed ADC/DAC and SerDes circuits, with deep understanding of timing, matching, shielding, and electromigration considerations. Hands‑on experience with Cadence Virtuoso tools (Layout, XL, PVS, Quantus) and solid understanding of schematic‑to‑layout (S2L) flow. Experience with FinFET and/or Gate‑All‑Around (GAA) process technologies. Strong understanding of analog layout techniques: current mirrors, differential pairs, resistors, capacitors, biasing, shielding, guard rings, and ESD structures. Experience leading tape‑outs, including design documentation, sign‑off checks, and cross‑team coordination. Good communication skills, both written and oral. The ability to articulate their thought process and lead junior members is important. This is a senior role. Prior job stability is mandatory – no job hoppers accepted. Master's in electrical engineering, Computer Engineering, or related field. Key Responsibilities: Own the physical layout design of high‑performance ADC/DAC, SerDes, and analog/mixed‑signal circuits across advanced nodes (2nm–16nm). Plan, and implement layout design for high‑speed, low‑noise analog blocks, ensuring signal integrity, matching, symmetry, and optimal parasitics. Closely collaborate with circuit designers to achieve aggressive power, performance, and area (PPA) targets, while maintaining design‑for‑manufacturability (DFM) best practices. Work with Cadence Virtuoso and Synopsys Verification tools to perform layout design, verification, and integration. Drive floorplanning and analog block partitioning, ensuring effective power grid design, guard ring placement, and substrate isolation techniques. Partner with foundry and CAD teams to optimize design flows for TSMC FinFET and Gate‑All‑Around (GAA) process nodes. Conduct LVS, DRC, ERC, and parasitic extraction (PEX) reviews and close layout verification loops. Participate in top‑level integration and tape‑out, ensuring all layout data and GDS handoffs meet sign‑off requirements. Provide technical mentorship to fellow engineers and help define layout design methodologies and automation improvements. Minimum Qualifications: 10+ years of industry experience in analog/mixed‑signal layout design in advanced process nodes (2nm–16nm, preferably TSMC). Proven track record designing layouts for high‑speed ADC/DAC and SerDes circuits, with deep understanding of timing, matching, shielding, and electromigration considerations. Hands‑on experience with Cadence Virtuoso tools (Layout, XL, PVS, Quantus) and solid understanding of schematic‑to‑layout (S2L) flow. Experience with FinFET and/or Gate‑All‑Around (GAA) process technologies. Strong understanding of analog layout techniques: current mirrors, differential pairs, resistors, capacitors, biasing, shielding, guard rings, and ESD structures. Experience leading tape‑outs, including design documentation, sign‑off checks, and cross‑team coordination. Strong analytical, problem‑solving, and communication skills. Self‑motivated engineer eager to work in a fast‑paced start‑up environment, adaptable to evolving project demands. Preferred Qualifications: Familiarity with Mentor/Siemens Calibre verification tools and scripting (Skill, Python, or Tcl) for layout automation. Exposure to floor planning and top‑level chip integration for complex mixed‑signal SoCs. Experience optimizing for signal integrity, IR drop, and thermal effects in high‑speed designs. #J-18808-Ljbffr