Product Development Engineer

## Product Development EngineerApplylocations: San Jose, California, United Statestime type: Full timeposted on: Posted Yesterdayjob requisition id: R02703# **Job Details:**### ## **Job Description:****About Altera**At AlteraTM, our independence as the world’s largest pure‐play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‐leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.**About the Role**Altera is searching for a **Product Development Engineer** to join our Manufacturing Content Development Engineering Group!The Manufacturing Content Development Engineering Group is responsible for architecting, developing, validating and productizing high quality manufacturing test content for FPGAs to screen out any manufacturing defects and thus guaranteeing the highest quality of outgoing parts to customers.**Key Responsibilities:*** Own manufacturing test content development for FPGA Reset and Configuration architectures, including Secure Device Manager (SDM), configuration interfaces, reset controllers, boot flows, and related infrastructure IPs.* Develop and implement DFT strategies utilizing Scan, ATPG, MBIST, IJTAG, and functional test methodologies to maximize fault coverage.* Perform pre-silicon test pattern simulation and validation to ensure test effectiveness prior to tape-out.* Collaborate with RTL, DFT, and Design Verification teams to ensure robust testability features are implemented early in the design cycle.* Analyze test results, debug silicon failures, and provide root cause analysis.* Work with manufacturing and test teams to optimize test time, cost, and quality.* Analyze early customer returns with emphasis on driving test hole closure activities.* Drive test time reduction through analysis of fallout data versus test time for various IPs to balance and drive overall product cost optimizations.* Stay updated with industry trends and emerging DFT/test technologies.**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.**$106,200 - $153,675 USD**We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.#LI-MD1### ## **Qualifications:****Minimum Qualifications:**Bachelor's Degree or Master's Degree in Electrical Engineering, or related field (or other related Engineering degree) with **5+ years of industry experience** in the following:* Experience in IC design and IC test.* Experience with FPGA Reset, Configuration, SDM, or DFX architectures.* Experience in DFT methodologies such as scan chains, Memory BIST, ATPG, boundary scan, test compression, IJTAG and JTAG networks* Experience with RTL design, synthesis, and verification flows.* Experience with fault grading, test time analysis, test coverage analysis, and test yield enhancement.* Scripting skills in Python, Perl, TCL, or similar.* Semiconductor manufacturing test processes.* Digital and analog circuit fundamentals.### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr