Principal Digital Engineer (DFT Design)

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world's leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what's next in electronics and the world. This is an opportunity to join a top-notch Power Management IC Team with Renesas leading Automotive Business Unit. You will be part of a very skilled group of engineers who are helping build world-class automotive PMIC products that will power tomorrow's automobiles. You will design complex chips that includes various analog and digital control circuitry and work very closely with all aspects of chip design – from writing specifications to developing tests for mass production. You will be a key contributor to the digital DFT design team and work closely with the digital design team for meeting TEST requirements for Automobile and work closely with test engineering teams for validating the test patterns and meeting ASIL-B/D requirements. You will have an opportunity to work on new designs, insert Lbist and shape the company's pathway for success. Your responsibilities, depending on your level of experience and skill level, will be a mix of the following: Inserting DFT/Scan on digital logic, ATPG, validating test patterns on pre and post layout gate level netlist. Delivering test patterns to TEST engineering team and validating them on silicon. Inserting Logicbist with industry standard tools. Improving scan coverage and modifying RTL for scan. Reduce ATE tester time by reducing scan patterns while achieving the required coverage. Participate in all aspects of digital design flow - Micro-architecture, Design partitioning, RTL Verilog / System Verilog coding, DFT insertion, generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC. Working closely with Architects, Design, P&R, Test and Silicon validation teams. Assisting with top level test-bench creation for scan and running gate level simulations. Debug scan pattern fails on ATE and fix the scan patterns. Writing detailed design documents and help writing DFT specifications, reviewing the specs with different stake holders and own the design to meet the spec. Organizing and participating in key design reviews and completion of various checklists. Working on-site for 3 days a week is a must. Following are rough guidelines for the qualifications (if you feel you have much more or somewhat less, let that not stop you from applying): Required Masters plus 12+ years or Bachelors plus 15+ years experience in digital design and DFT implementation. Must be a team player and yet be an independent thinker with strong digital design and DFT fundamentals Hands on experience in Scan insertion, improving scan coverage, ATPG, experience in Logicbist insertion during synthesis or rtl. Gate level simulations with test patterns, delivering test patterns to Test engineering team and work closely with them to get the patterns validated. Must have basic digital RTL coding experience besides synthesis exposure. Must have experience with at least 8 tapeouts with hands on experience with DFT/Scan. Ideal candidate will have solid understanding of synthesizable design, timing constraints and exceptions. Must have experience with industry standard Synopsys, Cadence, Mentor, Siemens for scan, Lbist insertion and ATPG. Tetramax experience is a huge plus. Attention to detail, accuracy and expertise in DFT required. Must have good written and verbal cross-functional communication skills Have an analytical mind - be open to new ideas and have capability to persuade others inconvincing and implementing better flows and processes. Desirable Mixed signal experience highly preferred. Exposure to automotive test requirements, ASIL, is highly preferred. Education BSEE required (MSEE preferred) Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world-leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas. #J-18808-Ljbffr Renesas Electronics