Senior Staff Engineer, Physical Implementation CAD Lead
$180.2k - $297.2kSamsung
Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role and Responsibilities As a Senior Staff Physical Implementation CAD Engineer, you will shape the development and deployment of physical design CAD flows and methodologies to enable high-performance, power-efficient GPU and SoC designs at advanced technology nodes. In this high-impact individual contributor role, you will lead a team of engineers focusing on physical implementation methodology innovation, while driving automation and scalable infrastructure across concurrent programs. You bring strong expertise in P&R tool ecosystems, bleeding-edge node challenges (<5nm), and cross-functional collaboration to improve flow robustness, design productivity, and PPA outcomes across Samsung’s next-generation silicon.
- Leveraging your expertise in physical design and CAD methodology, you define and evolve next-generation physical design flows (synthesis, placement, routing, timing, and power optimization) to enable scalable, high-quality design execution across advanced nodes.
- You provide technical leadership and hands-on support to project teams, driving flow triage, adapting methodologies to program-specific needs, and resolving complex implementation challenges through data-driven analysis.
- You champion automation and infrastructure development, building robust scripting and tool integrations (Python, Tcl, shell) while advancing AI-assisted methodologies to improve predictability, turnaround time, and engineering efficiency.
- You advance cross-functional collaboration with internal design and DTCO teams, and external EDA vendor partners to evaluate emerging technologies, influence tool capabilities, and proactively address new challenges introduced by sub-5nm process nodes.
- You inspire high performance by mentoring junior engineers, fostering a culture of ownership, accountability and innovation-driven execution, and staying ahead of emerging GPU physical implementation methodology and CAD best practices.
- 11+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 9+ years of experience with a Master’s Degree, or 7+ years of experience with a Ph.D.
- 11+ years of hands-on experience in Physical Design CAD, methodology development, or design enablement for complex GPU, CPU, or SoC programs.
- Strong expertise in Physical Design flows, including synthesis, place-and-route, timing closure, power optimization, and signoff methodologies.
- Deep experience with Cadence and/or Synopsys P&R toolsets, Static Timing Analysis, voltage-aware optimization, and voltage drop analysis.
- Strong understanding of advanced technology node challenges (<5nm), including physical verification flows (Calibre/ICV) and DTCO considerations.
- Proficiency in scripting and automation (Python, Tcl, shell) with experience building scalable CAD infrastructure.
- Experience with leading complex technical initiatives, driving process and methodology innovation, and mentoring engineers.
- Excellent collaboration and communication skills, with the ability to navigate ambiguity and influence in a fast-paced, global environment.
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$100k
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