Senior Software Engineer, Fleet-level ML Performance

Perform fleet-level performance analysis of key ML workloads (e.g., Gemini) on future TPU systems using advanced simulation tools to evaluate hardware/software trade-offs and guide next-generation chip architecture.Partner with teams across the ML stack including model researchers, compiler developers, systems engineers, and TPU architects to analyze and optimize performance across the design space.Design and implement a unified ML Accelerator Platform Performance Estimation Methodology using C++ and Python to enable scalable performance and TCO projections across Google.Collaborate cross-functionally with data center, hardware architecture, and framework teams to define key hardware and software requirements for future AI infrastructure.Minimum qualifications:Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field.5 years of experience in systems architecture or computer architecture, power and performance trade-off analysis, or data center, cloud, infrastructure hardware optimization .Experience with Reliability, Availability, and Serviceability (RAS) features, paradigms, or architecture.Preferred qualifications:Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.Knowledge of deep learning workloads, including embedding architectures and their hardware execution characteristics.Google Cloud’s mission is to make every business successful through AI by combining cutting-edge technology, infrastructure, and talent. AI/ML software engineers in Cloud bridge the gap between pioneering models and a massive product vehicle reaching billions. Our talent density and AI-powered tools drive rapid development, rooted in a culture of empowerment and a bias to action. In this role, you aren’t just building technology; you’re shaping the frontier of enterprise and driving the evolution of advanced models. The TPU Chip Architecture and Performance team bridges Google's machine learning workloads and custom silicon architectures. Through hardware/software co-design, we define and shape the future TPU platforms required to meet Google's ambitious AI goals. In this role, you will conduct end-to-end performance analysis of critical ML workloads including Gemini, YouTube, Ads, and key 3P models on next-generation TPU systems. Using advanced simulation and projection methodologies, you will evaluate hardware features and software optimizations to balance performance and cost trade-offs. You will drive high-impact architecture decisions that maximize TPU efficiency while accounting for system-wide constraints such as power, reliability (RAS), and scheduling.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $174000 - $252000 (USD) + 15% bonus target + equity + benefitsLearn more about benefits at Google.Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field.5 years of experience in systems architecture or computer architecture, power and performance trade-off analysis, or data center, cloud, infrastructure hardware optimization .Experience with Reliability, Availability, and Serviceability (RAS) features, paradigms, or architecture.