Principal Engineer-HIG HBM Architecture

About the Role You will be responsible for the design and development of next‑generation HBM DRAM products, working within a highly cross‑functional team of technical experts. The role involves collaborating closely with customers, partners, and internal teams from Engineering, Process Development, Package Engineering, and Business Units to define and develop innovative memory subsystem architectures. Key Responsibilities Develop innovative memory subsystem architectures for HBM‑based AI/ML solutions, including PHY, memory controllers, NOC, microcontrollers, MBIST, interfaces, adapters, RAS, and support for DDR/LPDDR/HBM memory types. Define memory and RAS architecture requirements and drive end‑to‑end architectural specifications for next‑generation memory subsystems. Collaborate with internal and external partners to develop novel architectures and detailed IP requirements across all memory subsystem components. Lead engagement with IP vendors, including evaluation and selection of interface IP and functional IP blocks. Analyze benchmarks, workloads, and simulation results to identify performance and efficiency innovation opportunities in memory subsystems. Perform performance and power modeling; estimate gate count, power, and area; and generate architectural and external‑facing specifications aligned with hardware/protocol standards. Partner with RTL, validation, and multi‑functional teams to ensure successful and timely implementation of subsystem features, contributing to technical reviews for HBM and memory products. Drive microarchitecture definition, participate in performance simulation and benchmarking, and debug issues across high‑level models, RTL simulation, and hard/soft IP. Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Minimum of 10 years of experience in memory subsystem architecture and design. Deep understanding of memory controller design and memory types (DDR, LPDDR, GDDR, HBM). Experience with PHY design and signal‑integrity issues. Proficiency in Network‑on‑Chip (NoC) architecture and design. Familiarity with industry‑standard bus protocols such as AXI, AMBA, AHB, DFI, HIF, etc. Strong analytical and problem‑solving skills. Excellent written and verbal communication skills. Preferred Qualifications A PhD in a relevant field, or equivalent experience. Familiarity with EDA tools for design and verification. Practical experience with multi‑core systems, coherent interconnects, and industry IO protocols such as PCIe/CXL, confidential compute, virtualization, and security. Knowledge of serial link protocols (e.g., UCIe) is desired. Compensation US base salary range: $146,000.00 – $309,000.00 per year. Compensation may include bonuses, equity, and additional benefits as described in the hiring process. Benefits Micron offers a comprehensive benefits package, including medical, dental, and vision plans, income protection, paid family leave, paid time‑off, and holidays. Equal Opportunity Employment Statement Micron is an equal‑opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws. Contact Information For job‑related inquiries, please refer to the Micron careers website or contact Micron’s People Organization at View email address on click.appcast.io. #J-18808-Ljbffr Micron Technology