Staff Engineer, TPU Co-Design

Google Sunnyvale, CA, USA Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in computer architecture, chip architecture, or hardware-software co-design. Experience developing systems for performance modeling, simulation, or system analysis. Preferred Qualifications Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience architecting hardware solutions or performance optimizations for large-scale ML training and inference. Experience with deep learning frameworks such as TensorFlow or PyTorch. Deep understanding of ML trends, business drivers, and the software ecosystem. Ability to engage and collaborate with hardware designers, software architects, and ML researchers. About the role In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU technology that powers Google’s most demanding AI/ML applications. You will be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s TPU, contributing to the innovation behind products loved by millions worldwide, and leveraging your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Staff Co-Design Engineer on the TPU Architecture team, you will act as a key technical anchor bridging the gap between model architecture innovation and next-generation hardware design. Operating cross-functionally across AI research and engineering, you will help shape the architectural roadmap for our future machine learning serving and training capabilities. You will drive the integration of ML research—such as the training and serving of massive foundation models—with advanced silicon architectures to deliver industry-leading, high-performance, and power-efficient accelerators. Responsibilities Drive the definition and optimization of the hardware/software stack to enable performant training and serving of large ML models. Collaborate with research and modeling teams to innovate on model architectures, focusing on scaling, quality, and their direct impact on hardware performance. Lead the development of configurable architectural simulators and cycle-accurate performance models to quantify microarchitectural optimizations and evaluate architectural decisions. Conduct system-level performance analysis across highly distributed ML systems, innovating new methodologies to balance compute, memory bandwidth, and inter-chip network requirements. Engage with partners across hardware design, compiler development, and ML research to transition architectural innovations from concept to production. Compensation Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: 192000 - 279000 USD + 20% bonus target + equity + benefits Legal and Diversity Statements Google is proud to be an equal-opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google’s EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire. English proficiency is a requirement for all roles unless stated otherwise in the job posting. #J-18808-Ljbffr Google Inc.