R&D Engineering, Principal Engineer

Category Engineering Hire Type Employee Job ID 18471 Base Salary Range $191000-$286000 Remote Eligible No Date Posted 08.26.2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performan ce silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are passionate about advancing the boundaries of electronic design automation (EDA) and static timing analysis (STA). Combining deep domain knowledge with practical hands-on experience, you thrive in architecting complex systems that impact the global semiconductor industry. You possess a strong sense of ownership, are comfortable navigating ambiguity, and excel at resolving the most challenging technical problems. Your expertise enables you to analyze system-level tradeoffs, balancing accuracy, scalability, and performance for mission-critic al sign-off flows. You are a collaborative influencer--va lued for your ability to mentor and guide both senior and junior engineers, and for your skill in articulating architectural direction that aligns with business goals and industry trends.

You are recognized for your proficiency in C/C++ and your ability to design and implement scalable, high-performan ce codebases. You are adept at identifying systemic issues and providing principled solutions, especially when working directly with customers on tapeout-critic al challenges. Your communication skills foster trust and inspire technical excellence across distributed teams. You are proactive in defining long-term strategies and have a proven track record of delivering impactful results in complex, fast-paced environments. Above all, you are driven by a desire to shape the future of silicon innovation, ensuring that the PrimeTime platform remains the industry standard for timing sign-off at advanced technology nodes.

What You'll Be Doing:

* Owning and evolving major architectural components of PrimeTime, including timing engines, path search frameworks, constraint modeling, and distributed/pa rallel analysis flows.
* Defining long-term technical strategy for accuracy, capacity, runtime, and extensibility in static timing analysis, collaborating closely with senior R&D leadership.
* Driving architectural consistency across PrimeTime, Fusion Compiler integration points, and broader sign-off ecosystems.
* Leading the design and implementation of next-generatio n STA algorithms addressing m ulti-billion-c ell designs, advanced timing effects, and non-linear behaviors.
* Resolving cross-cutting technical issues and making principled tradeoffs between accuracy, performance, memory footprint, and usability at sign-off.
* Acting as the go-to technical authority for customer escalations, sign-off discrepancies, and complex architectural challenges.
* Diagnosing systemic issues involving SDC i nterpretation, timing convergence, path pessimism/opti mism, and tool correlations across flows.
* Mentoring and influencing engineers through technical reviews, discussions, and leadership--ra ising the technical bar across the organization.

The Impact You Will Have:

* Shape the architectural direction of PrimeTime, ensuring it remains the industry-leadi ng STA solution for advanced silicon designs.
* Define how PrimeTime scales to meet the complexity and reliability demands of next-generatio n SoCs.
* Reduce customer risk at tapeout by delivering architectural correctness, p redictability, and performance.
* Serve as a technical pillar for a tool that is crucial to the success of global silicon innovation.
* Influence the technical roadmap for sign-off methodology, driving improvements across multiple product releases.
* Enhance collaboration across distributed teams, fostering a culture of technical excellence and innovation.
* Directly impact customer satisfaction by resolving tapeout-critic al issues and ensuring robust timing sign-off flows.

What You'll Need:

* MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent demonstrated industry expertise.
* 10 years + of experience in EDA, system software, or similarly demanding technical domains.
* Deep hands-on experience with STA or closely related timing/circuit analysis technologies.
* Expert-level proficiency in C/C++ within large, performance-cr itical codebases.
* Proven track record of architecting complex systems and defining multi-year technical initiatives.
* Strong foundation in algorithms, data structures, and numerical analysis applied at scale.
* Ability to independently define, justify, and drive technical strategy and architectural decisions.
* Preferred: Experience with PrimeTime, distributed computing, parallel STA, memory-scalabl e design, and advanced-node design challenges.

Who You Are:

* Strategic thinker with a strong sense of ownership and a ccountability.
* Collaborative influencer, able to mentor and inspire technical teams.
* Excellent communicator, capable of articulating complex technical concepts to diverse audiences.
* Resilient problem solver who thrives on tackling challenging, high-impact issues.
* Adaptable and proactive, comfortable working in fast-paced and evolving environments.
* Detail-oriente d yet able to see the bigger picture, balancing short-term needs with long-term vision.

The Team You'll Be A Part Of:

You will join a world-class R&D team dedicated to advancing the PrimeTime platform, collaborating with experts in static timing analysis, algorithm design, and EDA systems. The team is passionate about delivering innovative solutions that define industry standards for timing sign-off. Together, you will tackle complex architectural challenges, drive technical excellence, and shape the future of silicon design by enabling customers to achieve reliable and high-performan ce tapeouts.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

#TPG

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.