Hardware & Silicon Validation Senior Staff Engineer (Westborough)

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your ImpactThe Custom Cloud Solutions (CCS) Hardware Validation Group is responsible for ensuring the quality, reliability, and performance of next generation data center ASIC and SoC products spanning a diverse portfolio that includes cloud infrastructure, AI accelerators, network processors, NICs, custom ASICs, SSD controllers, CXL devices, and domain specific accelerators.The team owns end to end hardware validation, working across the product lifecycle from early silicon bring up through system level qualification. Our scope includes functional hardware validation, electrical characterization, high speed SERDES validation, and system/platform validation, all executed in advanced, fully instrumented hardware labs. The group validates complex, high-performance silicon and platforms across a wide range of critical technologies and interfaces, including Memory Subsystems (DDR, HBM, memory controllers), High Speed Interconnects (PCIe, Ethernet, CPRI, PAM4/NRZ), D2D interconnects, Storage, and IO (Flash and NVME, SSD controllers, USB) and System and Platform testing.What You Can Expect• Own the end‑to‑end validation strategy for DDR subsystems, from pre‑silicon planning through post‑silicon bring‑up, characterization, and production readiness.• Define validation scope, coverage metrics, and test methodologies for memory controllers, PHYs, and full memory subsystems, ensuring compliance with JEDEC specifications and internal quality standards.• Lead post‑silicon bring‑up and debug of complex memory systems, driving root‑cause analysis across silicon, firmware, signal integrity, power integrity, and test infrastructure domains.• Serve as the primary technical authority for DDR validation, providing guidance on architecture trade‑offs, risk mitigation, and design optimization.• Drive cross‑functional collaboration with architecture, RTL, PHY, SI/PI, firmware, system validation, and product engineering teams to resolve issues and influence design improvements.• Lead development and execution of stress, corner‑case, performance, and RAS testing across PVT conditions to ensure long‑term reliability and robustness.• Partner with firmware and software teams to define and validate training algorithms, diagnostics, error handling, and recovery mechanisms.• Present technical findings, risk assessments, and validation status to engineering leadership and program stakeholders, enabling data‑driven decision making.• Actively influence best practices in validation methodology, automation, and lab infrastructure, helping scale validation efficiency for future silicon generations.• Support customer‑facing debug and escalations when required, providing expert‑level analysis and guidance on memory‑related issues.What We're Looking For• Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 5–10 years of relevant industry experience; or Master’s degree and/or PhD in Computer Science, Electrical Engineering, or a related discipline with 3–5 years of professional experience.• Deep hands‑on expertise in DDR memory technologies including DDR4 and DDR5, covering protocol, timing, training, power management, and system‑level behavior.• Expert understanding of memory subsystem architecture, including controller, PHY, interconnect, training algorithms, error handling (ECC), and RAS features.• Extensive experience validating JEDEC memory standards, interpreting specifications, and ensuring compliance across process, voltage, temperature (PVT) corners.• Demonstrated expertise in post‑silicon bring‑up, validation, stress testing, and debug of memory subsystems at block, subsystem, and full‑chip levels.• Hands‑on experience with high‑speed lab equipment, including oscilloscopes, logic analyzers, protocol analyzers, and memory test platforms.• Ability to analyze waveform‑level issues related to signal integrity, timing margins, training failures, and data integrity.• Proficiency in C/C++ for embedded or bare‑metal firmware development to support memory bring‑up, training, diagnostics, and stress testing.• Strong experience developing Python‑based automation frameworks for functional, regression, stress, and manufacturing validation.• Experience leading validation strategy and test planning for DDR subsystems, including coverage definition and execution ownership.• Excellent written and verbal communication skills, with the ability to present technical findings clearly to engineering leadership and executive stakeholders.Expected Base Pay Range (USD)143,400 - 212,230, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at View email address on apply.placed-app.com Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.#LI-SA1SummaryLocation: Westborough, MAType: Full time