Senior DFT Engineer, Test Infrastructure, Google Cloud

Senior DFT Engineer, Test Infrastructure, Google Cloud Sunnyvale, CA, USA Job Level: Mid Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with DFT features (e.g., JTAG/MBIST/ATPG/HSIO), verification, functional validation. Experience with one of the scripting languages: Python, Perl, or TCL. Experience with ATE platforms (e.g., Teradyne UltraFlex or Advantest). Experience with SystemVerilog. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture. 10 years of experience in test engineering or product engineering. Experience with Scan/ATPG test development, especially with Streaming Scan Network (SSN)/Streaming Fabric techniques, or memory BIST test development and repair scheme implementation, including BISR/BIRA. Experience in testing Intellectual Property (IP) such as Phase-locked Loops (PLL), Process Voltage Temperature (PVT) sensors, thermal diodes, Process Monitor Ring Oscillator (PMRO), droop detector, aging sensor, and eFuse. Experience with PCIE, Double Data Rate (DDR) and HBM testing. About the job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You’ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As a DFT Test Engineer, you will work closely with various teams within the design process and with other engineers to deliver the confidence needed in the design of the chip. You will collaborate with the Functional Verification team to develop Design for Testing (DFT) environments, drive DFT strategy, and ensure our DFT solutions are properly verified for all usage scenarios. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We’re the driving team behind Google’s groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full‑time position is $156,000–$229,000 plus bonus, equity and benefits. Our salary ranges are determined by role, level and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience and relevant education or training. For more information about benefits at Google, visit the Google benefits portal. Responsibilities Engage with DFT and Design teams at early design stage to define requirements for ATE tests and manufacturing test flow. Generate and verify ATE patterns, including debug level, production level, characterization, High Voltage Screen (HVS), High‑Temperature Operating Life (HTOL), Electrical Stress on Environment (ESOE) etc. Run pattern playbacks (VTPSIM) on all delivered patterns prior to silicon arrival to ensure high quality of pattern delivery. Own pattern translations and integrate DFT verification into the overall ASIC design flow. Prepare silicon debug verification strategy, test plan and readiness for testers, and participate in post‑manufacturing silicon bring‑up tasks. Legal and Equal Opportunity Statements Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit are subject to Google's Applicant and Candidate Privacy Policy. Google is an equal opportunity and affirmative action employer committed to building a workforce representative of the users we serve. Discrimination on the basis of race, creed, color, religion, gender, sexual orientation, gender identity or expression, national origin, disability, age, genetic information, veteran or family status, criminal history, or other protected class is prohibited. See Google's EEO Policy for details. If you have a need that requires accommodation, please let us know by completing the Accommodations for Applicants form. English proficiency is a requirement for all roles unless stated otherwise. Google does not accept agency resumes. Please do not forward resumes to our jobs alias or other organizations. Google is not responsible for fees related to unsolicited resumes. #J-18808-Ljbffr Google