Gate-level Noise (Signal Integrity) / STA CAD Engineer
$129.3k - $194.7kApple Oakbrook
Role Number: 200692988Team: HardwareLocation: Austin; SunnyvalePosted: 2026-11-02SummaryImagine what you could do here! At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it!As a member of the CAD group, you will support the gate-level glitch noise and static timing analysis (STA) methodologies that ensure the signal integrity and robustness of Apple silicon across advanced technology nodes. In this role, you will learn and apply sign-off methodologies, margin models, and production CAD flows for crosstalk glitch and timing closure using industry-standard tools, under the guidance of senior engineers. You will work closely with CAD and physical design teams, assist with tool qualifications, help execute tapeout ECO tasks, and gain exposure to modern automation - including AI-agent workflows - used to scale analysis across our largest SOC designs.DescriptionIn this role, your primary responsibilities will include:Assist with applying established sign-off methodologies, noise margins, and tool qualification procedures for gate-level glitch noise and static timing analysis (STA), under senior engineer guidance.Run and maintain existing production CAD flows and scripts for core noise and STA tools, supporting constraint setup through tapeout sign-off.Help execute glitch noise analysis tasks - including checking glitch thresholds and propagation reports under supervision.Assist with root-cause analysis of crosstalk glitch and timing anomalies, learning to use established automated triage workflows and AI-agent pipelines.Work closely with design and physical design teams on noise/timing constraints and flow issues, escalating closure and waiver decisions to senior engineers.Help execute noise and timing ECO tasks to support design convergence toward tapeout.Participate in tool and version qualification activities, helping track QoR and performance data against golden baselines.Help maintain documentation and learn noise and STA best practices from the team.Minimum QualificationsBS in Electrical Engineering, Computer Engineering, or related technical discipline.Preferred Qualifications1-2 years of experience in CAD methodology, EDA support, or digital design.Foundational understanding of gate-level signal integrity concepts, including crosstalk glitch noise and static timing analysis (STA).Exposure to industry-standard SI and STA tools (e.g., PrimeTime-SI, Tempus, or equivalent) through coursework, internship, or self-study.Basic scripting skills in Python, Tcl, and/or Perl.Willingness to learn noise and timing sign-off and ECO concepts with team support.Ability to execute well-defined tasks with close guidance and mentorship.Coursework or project exposure to standard cell library noise characterization (e.g., CCSN) or SPICE simulation basics.Familiarity with place-and-route (P&R) concepts and physical design flow basics.Curiosity about AI/LLM-assisted workflows for CAD scripting, report parsing, or automated triage.Good communication skills and eagerness to learn.Pay & BenefitsAt Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $129,300 and $194,700, and your base pay will depend on your skills, qualifications, experience, and location.Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple BenefitsNote: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.EEO StatementApple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicantEEO StatementApple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicantAccessibilityAt Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.Learn about accessibility in Apple’s workplaceLearn about reasonable accommodations for job applicantsAccessibilityAt Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.Learn about accessibility in Apple’s workplaceLearn about reasonable accommodations for job applicantsApplication DeadlineApple accepts applications to this posting on an ongoing basis.Application DeadlineApple accepts applications to this posting on an ongoing basis.
$184.7k - $324.8k
...we found it!As a member of the CAD group, you will support the gate-level glitch noise and static timing analysis (STA) methodologies that ensure the signal integrity and robustness of Apple silicon... ..., under the guidance of senior engineers. You will work closely with CAD...SuggestedRelocation- Apple in Austin, TX is seeking a CAD-focused engineer to join the CAD group and support gate-level glitch noise and STA methodologies ensuring signal integrity of Apple silicon. You will learn sign-off methodologies, margin models, and production CAD flows for crosstalk...Suggested
- ...we found it! As a member of the CAD group, you will support the gate-level glitch noise and static timing analysis (STA) methodologies that ensure the signal integrity and robustness of Apple silicon... ..., under the guidance of senior engineers. You will work closely with CAD...Suggested
- Apple in Austin, TX is seeking a Gate-level Noise (Signal Integrity) / STA CAD Engineer to support gate-level glitch noise and STA methodologies across advanced silicon nodes. You will develop sign-off workflows, maintain production CAD flows, and collaborate with design...Suggested
$150.4k - $277.6k
...devices!In this role as a member of the STA CAD team, you will be an integral part of the effort to improve the... ..., maintain, and enhance existing gate-level STA flows for Apple silicon designs... ...of fundamentals in noise, cross-talk, variation and timing marginsKnowledge...SuggestedRelocation$150.4k - $277.6k
...of our best-in-class CAD Group, you will be part... ...methodologies and flows for gate-level as well as transistor-... ...will include IP / SOC signal EM analysis for clock... ...interposer thermal integrity, power switch and... ...of the world's leading engineers, and help us deliver the...Relocation- ...of our best-in-class CAD Group, you will be... ...dynamic IR analysis, signal/power grid extraction, STA timing, signal/power... ...improve power grid integrity.Identifying opportunities... ...in electrical engineering machine learning applications... ...extraction, timing, noise, simulation,...
- ...ROLE: In this role, as part of CAD Methodology team, you’ll have... ...detail-oriented timing analysis engineer with strong technical... ...circuit fundamentals. Proficient in STA methodologies for timing closure... ...design datasets.Support the integration of ML tools into AMD’s internal...
$140k - $190k
...RobertsPiper Companies is looking for a Signal Integrity Applications Engineer to join a global leader in high‑... ...technologies while providing senior‑level technical leadership to support the... ...tolerance analysis, materials behavior, and CAD modeling (ProE/SolidWorks preferred)...Remote work$174.4k - $261.6k
...Job Area: Engineering Group, Engineering... ...block-level implementation... ...power, PLL, and CAD teams to... ..., variation, noise, and robustness... ...validation, integration, or related work... ..., Clock gating and low-power... ...leakage power, Signal integrity and... ...closely with PLL, STA/timing, power...Work experience placementWork from home$175k - $308.5k
...key member of our best-in-class CAD Group, you will be part of... ...hands-on experience in power/signal EM analysis and/or IR analysis... ...include•Supporting transistor level power/signal EM and/or IR solutions... ...groups (Physical-design and integration, Circuit-design / Power / Technology...Relocation- ...DescriptionAs a Full Chip Integration Engineer, you will be... ...placements• Own chip level place and route (PnR),... ...with the implementation/CAD teams during the entire... ...Integration, EMIR (Drop/Noise), SIGEM Analysis, Formal... ...knowledge of Extraction and STA methodology and...
$184.7k - $277.6k
...efficiently.DescriptionAs a Signoff Engineer, you’ll ensure that all... ...completed on complex mixed-signal designs prior to tapeout. In... ...on our advanced Signoff CAD team, you’ll work on state-of... ...signoff methodologies at both the gate and transistor level. This includes, but isn’t...Relocation- ...Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team... ...Role: We are seeking a senior‑level, hands‑on CAD automation engineer to own and drive... ...automation, and workflow optimization Integrate and customize EDA tools to support...Full timeWork at officeImmediate start
- ...former Navy electrical engineers with a proven track... ...harness design, electrical integration, and system-level wiring architecture... ...to ensure reliable signal and power... ...or similar electrical CAD tools. Robotics or Autonomous... ...practices for managing noise, grounding, shielding...
- ...your career.THE ROLE: Our CAD team delivers automated... ...verification, and STA. 3D design and advance... ...Familiarity with chip- or system-level netlists and ability to... ...across AMD.Develop and integrate end-to-end AI... ...Masters degree in computer engineering/Electrical Engineering...
$184.7k - $324.8k
...the Hardware Technology CAD team, you’ll help... ...CPU, GPU, Analog/Mixed Signal and SOC designs by developing... ...looking for passionate engineers to join our team. In... ...static timing analysis (STA).- Working directly with... ...- extraction, timing, noise, physical verification,...Relocation$150.4k - $277.6k
...the Hardware Technology CAD team, you’ll help... ...CPU, GPU, Analog/Mixed Signal and SOC designs by developing... ...looking for passionate engineers to join our team. In... ...static timing analysis (STA).- Working directly with... ...- extraction, timing, noise, physical verification,...Relocation- ...been propelled by the top engineers in mixed-signal processing. Our rockstar team... ...a hands-on, highly driven CAD engineer to own and elevate... ...simulation flows, including DSPF integration, regressions, and... ...domains—DC, AC, transient, noise, and statistical analysis—along...Full timeWork at officeImmediate start
- ...Silicon Technologies group seeks a Signoff Engineer to drive complex mixed-signal signoff prior to tapeout. You will develop... ...analyses, and refine EDA flows across gate and transistor levels. You will partner with Design, CAD, and Technology teams to ensure tool readiness...
- Qualcomm in Austin, Texas is looking for a CPU Integration CAD engineer to join their Engineering Group. The successful candidate will work with cross-functional teams to build and support top-tier implementation tools and flows for custom CPUs. Applicants should have...
$184.7k - $324.8k
...Apple! We’re looking for an engineer who will bring passion... ...programming skills to our team of CAD engineers. You’ll develop... ...solutions for transistor level analysis on Analog, RF and mixed-signal designs.In this role, you... ..., S-parameters, Periodic noise, PSS simulations....Relocation$140k - $160k
...class team of scientists, engineers, and business... ...expertise in high-speed mixed-signal design to research, design... ...Quantum Engineering to integrate, deploy, and support... ...Responsibilities Design high level system architectures... ...systems for low phase noise, low spurious content,...Temporary workWork at office3 days per week- ...As part of our Silicon Engineering group, you’ll help design... ...will:- Lead different STA activities at the same... ...timed.- Assemble the top level design for STA ensuring... ....- Work with CAD and Vendors to constantly... ...such as cross-talk, OCV, noise, etc.Experience with scripting...
$159.1k - $215.3k
...around the world.The Satellite Systems Integration and Test team validates the complete communications... ....As a Senior Network Development Engineer, you will lead hands-on integration and... .... • Correlate RF conditions such as signal level, interference, link margin, channel...Permanent employmentWork experience placementLocal areaFlexible hours$166.6k - $296k
...to apply your engineering background to make... ...for senior level engineers to drive... ...opportunity to integrate and come-up... ...complex chips - from gates to GDS.Working... ...the industry CAD tools - Cadence... ...timing closure and noise avoidance /... ...experience in Power and Signal Integrity...Relocation$129.3k - $194.7k
...searching for a hardworking engineer to join our exciting... ...to execute design and integration tasks for the high... ....DescriptionAs an ASIC STA Engineer, you will have... ...Timing: Full chip and block level timing closure/... ...Design teams. Working with CAD and Flow teams to define...Relocation- ...Analog/Mixed Signal IP Engineering Program Manager Apple is seeking an experienced... ...teams, including SoC Integration, Technology/Library, SoC Design, SoC PD, SoC DV, CAD, software, and hardware to ensure... ...teams to ensure high-level achievements for IP development...
$175k - $308.5k
...Cellular ASIC Design Engineer, you'll develop... ...for integrated circuits across... ...at the block/IP-level and system-level... ...collaborating with CAD teams, IP teams... ...validation and STA vs spice... ...analog, mixed signal) and timing constraints... ...clock gating, power gating,...Relocation- ...Analog/Mixed-Signal IP Engineering Program Manager Imagine what you could... ...with AMS IP design and SoC Integration teams to drive high-impact development... ..., Design Verification and CAD Identify program risks... ...of silicon issues at the IP level, and develop mitigation...
Do you want to receive more vacancies?
Subscribe and receive similar vacancies to Gate-level Noise (Signal Integrity) / STA CAD Engineer. Be the first to apply!



