Senior ASIC Verification Engineer

Verification Engineer

• Develop verification environments, reference models, scoreboards, protocol monitors, coverage components, and assertions.

• Drive functional coverage closure, regression health, and sign-off readiness across simulation and formal results.

• Build verification infrastructure, regression and CI systems, and reuse strategy across IP, subsystem, and SoC levels.

• Apply and build AI-assisted verification capabilities for stimulus generation, regression triage, and coverage analytics.

• Review testbench architecture and debug methodology, and mentor junior engineers in verification methodology.

• Own verification planning and execution for complex blocks and subsystems, from test plan through sign-off.

• Translate design specifications into verification strategies, measurable coverage goals, and early identification of high-risk scenarios.

• Select verification methods for each problem, including constrained-random simulation, formal analysis, and directed testing.

Basic Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field, or 7+ years equivalent experience.

Minimum five years of professional experience in ASIC or SoC functional verification.

Hands-on expertise in SystemVerilog, UVM or formal testbench development and maintenance.

• Experience with metric-driven verification for planning, assertions, and functional coverage closure.

• Experience verifying complex digital control and datapath logic, including RTL and system-level debug.

Preferred Qualifications:

• Background in space-based communications, wireless communications, or modem, baseband, or DSP hardware.

• Experience verifying LDPC, FEC, framing, or beamforming logic using bit-accurate reference models and fixed-point analysis.

• Formal verification experience on production silicon, including connectivity, register maps, arbitration, CDC, or security properties.

• Experience with interconnect or NoC verification covering performance, bandwidth, QoS, and deadlock analysis.

• Experience verifying fault tolerance and reliability features such as ECC, redundancy schemes, or fault injection.

• Experience developing C-based or portable stimulus for SoC, CPU boot, and firmware-driven test scenarios.

• Experience applying AI, ML, or LLM tooling to stimulus generation, regression triage, or coverage analysis.