Senior ASIC Verification Engineer

Job Title: Senior ASIC Verification EngineerJob Location: Santa Clara, CA or Boston, MACompensation: $150K - $250K base DOE plus equityRequirements: ASIC/SoC Verification, RTL Verification, UVM / SystemVerilog, High-Speed Interconnects (Ethernet, UCIe, PCIe, CXL, UALink), Memory SubsystemPosition OverviewWe are seeking a highly skilled Senior ASIC Verification Engineer to join our dynamic team. This role is pivotal in ensuring the functionality and reliability of our ASIC products through thorough verification processes. The ideal candidate will possess extensive experience in verification methodologies and a deep understanding of complex SoC architectures. You will propose and setup the optimum verification methodology. You will be part of an early-stage startup working on an exciting product in the Artificial Intelligence/DataCenter space. The work involves learning advanced LLM in modern data centers and applications to design memory acceleration.Key ResponsibilitiesDevelop and execute verification plans for ASIC designsUtilize UVM and SystemVerilog for creating testbenches and simulationsAnalyze design specifications to ensure comprehensive coverageCollaborate with design engineers to understand design intent and provide feedbackPerform RTL verification and validate key components including memory subsystems and interconnect architecturesContribute to post-silicon validation efforts to ensure product performanceStay updated with industry trends and advancements in ASIC verification techniquesMentor junior engineers and provide guidance on best practicesQualificationsBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field5+ years of experience in ASIC/SoC verificationStrong expertise in UVM and SystemVerilogIn-depth knowledge of high-speed interconnects such as Ethernet, PCIe, UCIe, CXL, and UALinkFamiliarity with RTL verification methodologies and toolsExperience with memory subsystem design and verificationUnderstanding of advanced process nodes and their implications on designExcellent problem-solving skills and attention to detailStrong communication and teamwork abilitiesBenefitsCompetitive salary commensurate with experience including base salary, performance-based bonus, and early-stage equity grantComprehensive benefits including health, dental, vision, and life insuranceWell-equipped, sunny offices in Santa Clara, CA and Boston, MARelocation assistance and visa sponsorshipPerks include a daily lunch stipend, 401k match, and moreA collaborative, continuous-learning work environment with smart, dedicated colleagues engaged in developing the next generation of architecture for high-performance computing