Senior Multi‑GPU Signal Processing and System Architecture Engineer

We are seeking a self‑motivated senior engineer for the Aerial Omniverse Digital Twin team. This hire will own the design and implementation of the real‑time signal‑processing subsystem that converts physics‑based channel descriptions into received signals for large numbers of emulated devices, across systems of potentially thousands of interconnected GPUs. This position offers the opportunity to work on foundational technology for 5G and 6G network simulation, using NVIDIA's world‑class compute and interconnect platforms! What you'll be doing As a member of NVIDIA's Aerial team, you will design and implement GPU kernels that apply time‑varying, multi‑antenna channels to OFDM signals under hard real‑time deadlines. You will architect the inter‑cell data‑flow layer — ensuring that the information each cell needs to model interference from its neighbours is compressed, transported, and consumed within the available NVLink and NIC budgets at scale. You will work with the propagation engine and RAN stack teams to orchestrate the end‑to‑end simulation pipeline, ensuring that propagation updates, channel application, and stack execution remain synchronised across hundreds or thousands of GPUs. You will assess design and implementation trade‑offs between physical fidelity, latency, and system scalability. What we need to see PhD in high‑performance computing, computer architecture, signal processing, or wireless communications (or equivalent experience). 12+ years of proven experience. Proficiency in CUDA kernel design with attention to memory hierarchy, register pressure, and HBM bandwidth planning, with a track record of writing production‑quality GPU code that meets hard real‑time deadlines. Demonstrated ability to build and reason about data flows across multi‑device GPU systems (NVLink, NIC/RDMA) with explicit bandwidth and latency accounting. Working knowledge of OFDM signal processing and the 5G NR physical layer, sufficient to implement and validate a channel‑emulation pipeline. Impactful publications involving GPU‑accelerated numerical workloads or real‑time system design. Ways to stand out from the crowd Experience with GPU‑accelerated RAN platforms, L1/L2 software stacks, or channel emulators. Knowledge of high‑bandwidth GPU interconnects (NVLink, NVSwitch) and their scaling properties. Familiarity with massive MIMO beamformer design and MU‑MIMO precoding. If you're eager to contribute to crafting the future of telecommunications and meet the above qualifications, we’d love to hear from you. Submit your application and join NVIDIA as we continue to push the boundaries of what’s possible. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 200,000 USD - 322,000 USD for Level 5, and 248,000 USD - 396,750 USD for Level 6. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until April 28, 2026. This posting is for an existing vacancy. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr NVIDIA