Sr. Analyst-CAE (San Jose)

Job ID: SRJ_6883Posted: 2025-03-06Location: San Jose, CASalary: USD 35-55 / Hourly (C2C)Employment Type: Full TimeClient: TechMContact: Meghana GorusuCompany: SRI Tech SolutionsJob Title: Sr. Analyst-CAELocation: San Jose, California (Only local Candidate)Onsite/ Remote: Day 1 Onsite at customer location Skills: Place and Route (PnR) Expert – ASIC Design (Cadence Genus, Innovus, Tempus, iSpatial)Job Description: Sr. Analyst-CAEWe are looking for a Place and Route (PnR) Expert to drive the physical implementation of ASIC blocks, ensuring robust timing closure and adherence to physical constraints. The ideal candidate will have hands-on experience with Cadence Genus, Innovus, Tempus, and iSpatial flows, enabling a seamless transition from synthesis to final layout. This role involves optimizing performance, power, and area (PPA) while ensuring Design Rule Check (DRC) and Layout vs. Schematic (LVS) compliance.Key Responsibilities:Perform floor planning, placement, clock tree synthesis (CTS), routing, and optimization for ASIC blocks.Use Cadence iSpatial to establish a unified synthesis-to-place-and-route flow for efficient physical implementation.Ensure timing closure using Tempus STA, resolving setup, hold, clock skew, and noise violations.
Apply physical constraints, including placement constraints, routing blockages, and power grid definition.Work on congestion analysis, IR drop analysis, and signal integrity optimization to meet design signoff requirements.Conduct physical verification (DRC, LVS, antenna checks) and implement necessary fixes.
Collaborate with RTL designers, DFT engineers, and verification teams to ensure seamless integration.Perform Engineering Change Order (ECO) implementation to address functional and timing updates.
Develop and enhance automation scripts (TCL, Python, Perl) for workflow efficiency.Optimize power planning strategies to minimize leakage and dynamic power.
Keep up to date with Cadence tool advancements and apply best practices in leading-edge node technologies (e.g., 7nm, 5nm, 3nm FinFETs).Required Qualifications:Bachelor’s/Master’s degree in Electrical Engineering, VLSI, or a related field.5+ years of hands-on experience in ASIC Place & Route using Cadence Genus, Innovus, Tempus, and iSpatial flows.Strong expertise in timing analysis, static timing closure, and signoff methodologies.Proficiency in floorplanning, placement, CTS, and routing optimizations.Experience with power planning, IR drop mitigation, and clock tree balancing.Familiarity with Cadence Quantus for extraction and Pegasus/Calibre for physical verification.Strong scripting skills (TCL, Python, Perl) to automate design tasks.Understanding of DFT integration and multi-mode, multi-corner optimization strategies.Ability to work in a fast-paced, cross-functional team environment.Preferred Qualifications:
Experience with leading-edge finfet process nodes (16nm, 12nm, 5nm, 3nm, or below).SRI Tech Solutions is an equal opportunity employer and does not discriminate on the basis of race, color, gender, religion, age, sexual orientation, national origin or citizenship status or ethnic origin, disability, marital status, veteran status, or any other occupationally irrelevant criteria.