Datacenter Server CPU Platform Architect

Datacenter Server CPU Platform Architect

Category

Algorithm & Architecture

Location

San Jose, CA

Experience

More than 8 Years Work Expe.

Job Description

MediaTek’s Data Center team is at the forefront of innovation, driving the development of cutting-edge technologies that power the world's most advanced data centers. We are a dynamic group of system architects, packaging technology developers, and SoC design experts dedicated to creating high-performance, efficient, and reliable solutions. Our team collaborates closely to push the boundaries of technology, ensuring optimal performance, power efficiency, and scalability for data center applications. Join our Data Center team and be a part of the technological revolution that is shaping the future of data centers. If you are passionate about innovation and have the expertise to drive strategic technology development, we would love to hear from you.

Role SummaryWe are looking for a visionary Datacenter Compute Platform Architect to enable our cutting-edge silicon on the platform. While our SoC architects focus on what goes inside the chip, you will be the owner of the system that surrounds it. In this role, you will define the end-to-end server platform architecture, ensuring our CPUs operate at peak performance, efficiency, and reliability within cloud infrastructure. You will drive hardware specifications spanning power delivery, thermal management, memory topologies, high-speed I/O routing, and system management. You will work closely with internal silicon teams, firmware engineers, and external OEM/ODM partners and hyperscale customers to bring next-generation compute platforms from concept to mass deployment.

Key Responsibilities

• Platform Architecture Definition: Define the compute system architecture (workstation, 1U/2U, multi-node, OCP form factors) surrounding our Datacenter compute SoC.
• Power & Thermal Management: Architect system-level power delivery networks (PDN/VRM specs) and collaborate on advanced thermal solutions (air and liquid cooling) to meet strict datacenter TDP constraints.
• High-Speed I/O & Memory: Define system-level topologies and routing guidelines for high-speed interfaces, including LP/DDR5/6, PCIe Gen 5/6, and CXL. Ensure Signal Integrity (SI) and Power Integrity (PI) targets are met at the board level.
• Server Management & Security: Define architectures for Baseboard Management Controllers (BMC), OpenBMC integration, hardware Root of Trust (RoT), and system-level security (e.g., SPDM, TPMs).
• Firmware/OS Co-Design: Partner with SoC silicon, BIOS/UEFI, OS, and firmware teams to define ACPI tables, RAS (Reliability, Availability, and Serviceability) flows, and power management states.
• Ecosystem & Partner Enablement: Act as the primary technical interface for Tier-1 ODMs, OEMs, and Cloud Service Providers (CSPs) to ensure successful platform design, validation, and deployment.

Location: open to San Jose, San Diego, Portland and Austin#LI-WC2

Main Requirements and Qualifications

• Qualifications
• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Industry Experience: 10+ years of experience in server system architecture, motherboard design, or datacenter hardware engineering.
• Hardware Expertise: Deep understanding of x86, ARM, or RISC-V server/SoC architectures, AI compute engine, multi-socket topologies, and enterprise-grade hardware design.
• Interfaces & Standards: Expert knowledge of datacenter connectivity standards, including PCIe, CXL, Ethernet, and memory technologies (DDR4/5, LPDDR). Strong background in guiding SI/PI teams and understanding the physical limitations of high-speed PCB design.
• System Management: Solid understanding of server manageability standards (IPMI, Redfish, NC-SI) and BMC architectures. Hands-on experience defining end-to-end RAS (Reliability, Availability, Serviceability) architectures.
• Communication: Proven ability to write detailed platform specifications and present complex system-level trade-offs to both silicon designers and external customers.
• Advanced System Design: Experience with Open Compute Project (OCP) specifications (e.g., OAM, DC-MHS) and modern hyperscaler rack architectures.
• Advanced Packaging/Chiplets: Understanding of how multi-die/chiplet SoC architectures impact system-level power delivery and thermal dissipation.
• Salary range: $211,000- $356,000
• Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more.
• MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.